Dong Uk Lee, Hyun-Woo Lee, Ki Chang Kwean, Young-Kyoung Choi, Hyong Uk Moon, Seung-Wook Kwack, Shin-Deok Kang, Kwan-Weon Kim, Yong-Ju Kim, Young-Jung Choi, Patrick B. Moran, Jin-Hong Ahn, Joong Sik Kih. A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL. In 2006 IEEE International Solid State Circuits Conference, ISSCC 2006, Digest of Technical Papers, an Francisco, CA, USA, February 6-9, 2006. pages 547-556, IEEE, 2006. [doi]
Abstract is missing.