Shuichi Tahara - researchr alias

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Viewing Publication 1 - 8 from 8

2007

TD: Emerging Devices Devices and CircuitsEugenio Cantatore, Shuichi Tahara. isscc 2007: 60-61 [doi]

Writing Circuitry for Toggle MRAM to Screen Intermittent Failure ModeTakeshi Honda, Noboru Sakimura, Tadahiko Sugibayashi, Naoki Kasai, Hiromitsu Hada, Shuichi Tahara. ieicet, 90-C(2):531-535, 2007. [doi]

MRAM Cell Technology for Over 500-MHz SoCNoboru Sakimura, Tadahiko Sugibayashi, Takeshi Honda, Hiroaki Honjo, Shinsaku Saito, Tetsuhiro Suzuki, Nobuyuki Ishiwata, Shuichi Tahara. jssc, 42(4):830-838, 2007. [doi]

MRAM Applications Using Unlimited Write EnduranceTadahiko Sugibayashi, Takeshi Honda, Noboru Sakimura, Shuichi Tahara, Naoki Kasai. ieicet, 90-C(10):1936-1940, 2007. [doi]

2006

A 16Mb MRAM with FORK Wiring Scheme and Burst ModesYoshihisa Iwata, Kenji Tsuchida, Tsuneo Inaba, Yui Shimizu, R. Takizawa, Yoshihiro Ueda, Tadahiko Sugibayashi, Yoshiaki Asao, Takeshi Kajiyama, Keiji Hosotani, Sumio Ikegawa, Tadashi Kai, M. Nakayama, Shuichi Tahara, Hiroaki Yoda. isscc 2006: 477-486 [doi]

2003

3) architecture for a burst operated 1.5V MRAM macroTsuneo Inaba, Kenji Tsuchida, Tadahiko Sugibayashi, Shuichi Tahara, Hiroaki Yoda. cicc 2003: 399-402 [doi]

1989

570-ps 13-mW Josephson 1-kbit NDRO RAMShuichi Nagasawa, Yoshifusa Wada, Mutsuo Hidaka, Hisanao Tsuge, Iichiro Ishida, Shuichi Tahara. jssc, 24(5):1363-1371, October 1989. [doi]

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