Don Plass - researchr alias

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Viewing Publication 1 - 6 from 6

2012

Isolated Preset Architecture for a 32nm SOI embedded DRAM macroJohn Barth, Don Plass, Adis Vehabovic, Rajiv V. Joshi, Rouwaida Kanj, Steven Burns, Todd Weaver. vlsic 2012: 110-111 [doi]

2011

A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 CacheJohn Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael Sperling, Abraham Mathews, Toshiaki Kirihata, William R. Reohr, Kavita Nair, Nianzheng Caon. jssc, 46(1):64-75, 2011. [doi]

2010

A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cacheJohn Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael Sperling, Abraham Mathews, William R. Reohr, Kavita Nair, N. Cao. isscc 2010: 342-343 [doi]

2008

An on-chip dual supply charge pump system for 45nm PD SOI eDRAMJente B. Kuang, A. Mathews, J. Barth, Fadi H. Gebara, T. Nguyen, Jeremy D. Schaub, Kevin J. Nowka, Gary D. Carpenter, Don Plass, E. Nelson, Ivan Vo, William R. Reohr, Toshiaki Kirihata. esscirc 2008: 66-69 [doi]

2006

A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM ProcessorJohn Davis, Don Plass, Paul Bunce, Yuen H. Chan, Antonio Pelella, Rajiv V. Joshi, A. Chen, William V. Huott, Thomas J. Knips, Pradip Patel, K. Lo, Eric Fluhr. isscc 2006: 2564-2571 [doi]

2000

Design validation of .18 μm 1 GHz cache and register arraysDoug Malone, Paul Bunce, Joe DellaPietro, John Davis, James Dawson, Thomas J. Knips, Don Plass, Phil Pritzlaff, Kenneth Reyer. cicc 2000: 295-298 [doi]

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