Table of Contents

• 142 dB ΔΣ ADC with a 100 nV LSB in a 3 V CMOS processRavindranath Naiknaware, Terri S. Fiez. 5-8 [doi]
• A 20 bit 25 kHz delta sigma A/D converter utilizing frequency-shaped chopper stabilization schemeChris Binan Wang. 9-12 [doi]
• A 1 V 1 mW digital-audio ΔΣ modulator with 88 dB dynamic range using local switch bootstrappingMohamed Dessouky, Andreas Kaiser. 13-16 [doi]
• An audio ADC delta-sigma modulator with 100 dB SINAD and 102 dB DR using a second-order mismatch-shaping DACEric Fogleman, Jared Welz, Ian Galton. 17-20 [doi]
• A 12-bit 12.5 MS/s multi-bit ΔΣ CMOS ADCYves Geerts, Michiel Steyaert, Willy Sansen. 21-24 [doi]
• A 8.75-MBaud single-chip digital QAM modulator with frequency-agility and beamforming diversityKyung-Ho Cho, Henry Samueli. 27-30 [doi]
• Direct digital frequency synthesis of low-jitter clocksDorin Emil Calbaza, Yvon Savaria. 31-34 [doi]
• A 2-V 3.7-mW delay locked-loop using recycling integrator correlators for a 5-Mcps DS-CDMA demodulatorYoshihisa Fujimoto, Shuichi Kawama, Kunihiko Iizuka, Masayuki Miyamoto, Daniel Senderowicz. 35-38 [doi]
• rd generation W-CDMA systemsHiroshi Suzuki, Zhongfeng Wang, Keshab K. Parhi. 39-42 [doi]
• High-performance flexible all-digital quadrature up and down converter chipRobert Pasko, Luc Rijnders, Patrick Schaumont, Serge Vernalde, Daniela Duracková. 43-46 [doi]
• CMOS in the new millenniumTak H. Ning. 49-56 [doi]
• Ultra low-power CMOS IC using partially-depleted SOI technologyAkihiko Ebina, Tadao Kadowaki, Yoko Sato, Masayuki Yamaguchi. 57-60 [doi]
• A fabrication method for high performance embedded DRAM of 0.18 μm generation and beyondT. Yoshida, H. Takato, T. Sakurai, K. Kokubun, K. Hiyama, A. Nomachi, Y. Takasu, M. Kishida, H. Ohtsuka, H. Naruse, Y. Morimasa, N. Yanagiya, T. Hashimoto, T. Noguchi, T. Miyamae, N. Iwabuchi, M. Tanaka, J. Kumagai, H. Ishiuchi. 61-64 [doi]
• NV-SRAM: a nonvolatile SRAM with back-up ferroelectric capacitorsTohm Miwa, Junichi Yamada, Hiroki Koike, Hideo Toyoshima, Kazushi Amanuma, Sota Kobayashi, Tom Tatsumi, Yukihiro Maejima, Hiromitsu Hada, Takemitsu Kunio. 65-68 [doi]
• TM microprocessorJayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham. 71-74 [doi]
• Modular test generation and concurrent transparency-based test translation using gate-level ATPGYiorgos Makris, Alex Orailoglu, Praveen Vishakantaiah. 75-78 [doi]
• Diagnosing resistive bridges using adaptive techniquesJayabrata Ghosh-Dastidar, Nur A. Touba. 79-82 [doi]
• A stand-alone integrated excitation/extraction system for analog BIST applicationsMohamed M. Hafed, Gordon W. Roberts. 83-86 [doi]
• A new design for complete on-chip ESD protectionAlbert Z. Wang. 87-90 [doi]
• Cell characterization for noise stabilityKenneth L. Shepard, K. Chou. 91-94 [doi]
• Quantitative characterization of substrate noise for physical design guides in digital circuitsMakoto Nagata, Jin Nagai, Takashi Morie, Atsushi Iwata. 95-98 [doi]
• Improving embedded software design and integration in SOCsGrant Martin, Christopher K. Lennard. 101-108 [doi]
• Coral-automating the design of systems-on-chip using coresReinaldo A. Bergamaschi, William R. Lee, Duane Richardson, Subhrajit Bhattacharya, Michael Muhlada, Ronaldo Wagner, Arthur Weiner, Foster White. 109-112 [doi]
• Wire planning for performance and yield enhancementCharles Ouyang, Kyungsuk Ryu, Hans Heineken, Jitu Khare, Saghir A. Shaikh, Manuel d'Abreu. 113-116 [doi]
• Probabilistic aspects of crosstalk problems in CMOS ICsCristinel Ababei, Radu Marculescu, Venkat Sundarajan. 117-120 [doi]
• Applying placement-based synthesis for on-time system-on-a-chip designDavid E. Lackey. 121-124 [doi]
• Methodology for I/O cell placement and checking in ASIC designs using area-array power gridPatrick H. Buffet, Joseph Natonio, Robert A. Proctor, Yu H. Sun, Gulsun Yasar. 125-128 [doi]
• Architecture of cluster-based FPGAs with memoryJason P. Clifford, Steven J. E. Wilton. 131-134 [doi]
• TM. A memory-rich, high performance, scalable CPLD architectureAndrew Kennings, Haneef Mohammed, Joseph P. Skudlarek, Bing Tian. 135-138 [doi]
• Dynamic clock management for low power applications in FPGAsIan Brynjolfson, Zeljko Zilic. 139-142 [doi]
• A million gate PLD with 622 MHz I/O interface, multiple PLLs and high performance embedded CAMSammy Cheung, Kar Keng Chua, Boon-Jin Ang, Thow Pang Chong, Wei Lian Goay, Wei-Yee Koay, Sin Wo Kuan, Chooi Pei Lim, Jiunn Shyong Oon, Theam Thye See, Chiakang Sung, Kim Pin Tan, Yu Fong Tan, Choong Kit Wong. 143-146 [doi]
• Parallel and scalable architecture for solving SATisfiability on reconfigurable FPGATarachand Pagarani, Fatih Kocan, Daniel G. Saab, Jacob A. Abraham. 147-150 [doi]
• Spatial-temporal mapping of real applications on a Dynamically Reconfigurable Logic Engine (DRLE) LSIKoichiro Furuta, Taro Fujii, Masato Motomura, Kazutoshi Wakabayashi, Masakazu Yamashina. 151-154 [doi]
• Field configurable system-on-chip device architectureSteve Knapp, Danesh Tavana. 155-158 [doi]
• CMOS RF design-the low power dimensionQiuting Huang. 161-166 [doi]
• A low-power CMOS super-regenerative receiver at 1 GHzAlexandre Vouilloz, Catherine Dehollain, Michel J. Declercq. 167-170 [doi]
• A 1 V, 1 mW, 434 MHz FSK receiver fully integrated in a standard digital CMOS processAlain-Serge Porret, Thierry Melly, Dominique Python, Christian C. Enz, Eric A. Vittoz. 171-174 [doi]
• A dual-band RF front-end for WCDMA and GSM applicationsJussi Ryynänen, Kalle Kivekäs, Jarkko Jussila, Aarno Pärssinen, Kari Halonen. 175-178 [doi]
• A 1.2 V, 433 MHz, 10 dBm, 38% global efficiency FSK transmitter integrated in a standard digital CMOS processThierry Melly, Alain-Serge Porret, Christian C. Enz, Eric A. Vittoz. 179-182 [doi]
• Frequency-scalable SiGe bipolar RFIC front-end designOsama Shana'a, Ivan Linscott, Len Tyler. 183-186 [doi]
• MOS transistor modeling for RF integrated circuit designChristian C. Enz. 189-196 [doi]
• BSIMPD: a partial-depletion SOI MOSFET model for deep-submicron CMOS designsPin Su, Samuel K. H. Fung, Stephen Tang, Fariborz Assaderaghi, Chenming Hu. 197-200 [doi]
• New paradigm of predictive MOSFET and interconnect modeling for early circuit simulationYu Cao 0001, Takashi Sato, Michael Orshansky, Dennis Sylvester, Chenming Hu. 201-204 [doi]
• RFCMOS extension model accurate up to 40 GHz with distributed junction diodeTimothy C. Kuo. 205-208 [doi]
• Advanced compact model for short-channel MOS transistorsOscar da Costa Gouveia-Filho, Ana Isabele Araujo Cunha, Márcio Cherem Schneider, Carlos Galup-Montoro. 209-212 [doi]
• S-TFT: an analytical model of polysilicon thin-film transistors for circuit simulationGi-Young Yang, Yeong-Gil Kim, Taek-Soo Kim, Jeong-Taek Kong. 213-216 [doi]
• A 64 min single-chip voice recorder/player using embedded 4 bit/cell flash memoryMichele Borgatti, Alessandro Rocchi, Marco Bisio, Monica Besana, Loris Navoni, Pier Luigi Rolandi. 219-222 [doi]
• A low-power system-on-chip for the documentation of road accidentsLuca Bolcioni, Roberto Guerrieri. 223-226 [doi]
• Designing high-speed serial ports using standard ASIC library elements, tools and design methodologiesPaul Freud. 227-230 [doi]
• A 9-M tr. access network system-on-a-chip for mega-bit Internet access at homeShinichi Kozu, Toshiya Aramaki, Chinatsu Ikeda, Yasuaki Kuroda, Satoru Kawanago, Mitsuji Okada, Hiroshi Kariya, Masao Manabe, Hirotaka Utani, Eiji Sudou, Yukihiro Oda, Hideo Suzukii. 231-234 [doi]
• A 300 K-gate 0.5 μm CMOS implementation of an 8-VSB receiver IC [for HDTV]Ilwan Lee, Dongkyu Kim, Seokjun Lee, Kipaek Kwon, Jongdae Kim, Incheol Kim, Yongho Kim, Sungjun Park, Cheongon Kim, Haemook Jung, Gyuhwan Chang. 235-238 [doi]
• Secure contactless smartcard ASIC with DPA protectionPatrick Rakers, Larry Connell, Tim Collins, Dan Russell. 239-242 [doi]
• A broadband 10 GHz track-and-hold in Si/SiGe HBT technologyJonathan C. Jensen, Lawrence E. Larson. 245-248 [doi]
• A 6-bit 1 GHz acquisition speed CMOS flash ADC with digital error correctionKoen Uyttenhove, Augusto Marques, Margot Steyaert. 249-252 [doi]
• A 100-MSPS 8-b CMOS subranging ADC with parametric operation from 3.8 V down to 2.2 VRobert C. Taft, Maria Rosaria Tursi. 253-256 [doi]
• A 10-bit, 3 V, 100 MS/s pipelined ADCDavid G. Nairn. 257-260 [doi]
• A highly linear low-power 10 bit DAC for GSMPaul F. Ferguson Jr., Xavier Haurie, Gabor C. Temes. 261-264 [doi]
• A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converterAnne Van den Bosch, Melissa Borremans, Michiel Steyaert, Willy Sansen. 265-268 [doi]
• Design methodology of the embedded DRAM with the virtual socket architectureMitsuya Kinoshita, Tadaaki Yamauchi, Teruhiko Amano, Katsumi Dosaka, Kenshin Arimoto. 271-274 [doi]
• Low-power technique for on-chip memory using biased partitioning and access concentrationNaoyuki Kawabe, Kimiyoshi Usami. 275-278 [doi]
• A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory cell efficiency of 33%Yuji Yokoyama, Nybutaka Itoh, Masap Katayama, Kazumasa Takashima, Hiroshi Akasaki, Masayuki Kaneda, Toshitsugu Ueda, Yousuke Tanaka, Eiji Yamasaki, Masaya Todokoro, Keinosuke Toriyama, Hiroshi Miki, Masayoshi Yagyu, Tom Kobayashi, Syuichi Miyaoka, Nobuo Tamba. 279-282 [doi]
• An ultra-high-density high-speed loadless four-transistor SRAM macro with a dual-layered twisted bit-line and a triple-well shieldKenji Noda, Koujirou Matsui, Shinya Ito, Sadaaki Masuoka, Hiroyuki Kawamoto, Nobuyuki Ikezawa, Koichi Takeda 0001, Yoshiharu Aimoto, Naoto Nakamura, Hideo Toyoshima, Takahiro Iwasaki, Tadahiko Horiuchi. 283-286 [doi]
• SRAM embedded memory with low cost, flash EEPROM-switch-controlled redundancyRichard J. McPartland, D. J. Loeper, Frank P. Higgins, Raj Singh, G. MacDonald, Goh Komoriya, S. Aymeloglu, M. V. DePaolis, C. W. Leung. 287-289 [doi]
• Embedded DRAM: an element and circuit evaluationPhilip W. Diodato, J. H. O'Neill, Y. H. Wong, G. B. Alers, H. M. Vaidya, S. Chaudhry, W. S. Lindenberger, A. C. Dumbri, C. T. Liu, W. Y.-C. Lai. 291-294 [doi]
• Design validation of .18 μm 1 GHz cache and register arraysDoug Malone, Paul Bunce, Joe DellaPietro, John Davis, James Dawson, Thomas J. Knips, Don Plass, Phil Pritzlaff, Kenneth Reyer. 295-298 [doi]
• A CMOS ADSL codec for central office applicationsPatrick P. Siniscalchi, Jeanne K. Pitz, Richard K. Hester, Stewart DeSoto, Minsheng Wang, Sucheedran Sridharan, Robert L. Halbach, Donald Richardson, William Bright, Maher M. Sarraj, James R. Hellums, Christopher L. Betty, Glenn H. Westphal. 303-306 [doi]
• A 4 channel analog front end for central office ADSL modemsJohn Kenney, Faramarz Sabouri, Vincent Leung, John Guido, Ed Zimany, Anthony Agrillo, Joseph Trackim, John Khoury, Reza Shariatdous. 307-310 [doi]
• A single-chip universal burst receiver for cable modem/digital cable-TV applicationsFang Lu, Jonathan S. Min, Sam Liu, Kelly Cameron, Christopher Jones, Owen Lee, Johnson Li, Aaron Buchwald, Stephen Jantzi, Christopher Ward, Kenneth Choi, Jim Searle, Henry Samueli. 311-314 [doi]
• A single chip 155 Mbps/140 Mbps SDH/PDH transceiverJesus Guinea, Luciano Tomasini, Santo Maggio, Massimiliano Rutar. 315-318 [doi]
• A 450 Mbit/s parallel read/write channel with parity check and 16-state time variant ViterbiGiacomino Bollati, Angelo Dati, Giorgio Betti, Ivan Bietti, Francesco Brianti, Melchiorre Bruccoleri, M. Coltella, P. Demartini, Marco Demicheli, Paolo Gadducci, Stefano Marchese, Daniele Ottini, Valerio Pisati, Francesco Rezzi, A. Rossi, P. Savo, C. Tonci, Rinaldo Castello. 319-322 [doi]
• A versatile low-power power line FSK transceiverRoberto Cappelletti, Andrea Baschirotto. 323-326 [doi]
• An analog front-end LSI with on-chip isolator for V.90 56 kbps modemsNobuyasu Kanekawa, Yasuyuki Kojima, Seigo Yukutake, Minehiro Nemoto, Takayuki Iwasaki, Kazuhisa Takami, Yusuke Takeuchi, Atsuko Yano, Yasuo Shima. 327-330 [doi]
• Silicon radio integration: architectures and technology: from cartesian zero IF receive & transmit to polar zero I and Q, from silicon bipolar to bulk and SOI CMOSJan Sevenhans. 333-340 [doi]
• A 900-MHz T/R switch with a 0.8-dB insertion loss implemented in a 0.5-μm CMOS processFeng-Jung Huang, Kenneth K. O. 341-344 [doi]
• Stacked inductors and 1-to-2 transformers in CMOS technologyAlireza Zolfaghari, Andrew Chan, Behzad Razavi. 345-348 [doi]
• An integrated capacitively coupled transformer and its application for RF IC'sLai-Pong (Lawrence) Wong, Chris Snyder, Tajinder Manku, Stephen Kovacic. 349-352 [doi]
• Measuring and modeling the effects of substrate noise on the LNA for a CMOS GPS receiverMin Xu, David K. Su, Derek K. Shaeffer, Thomas H. Lee, Bruce A. Wooley. 353-356 [doi]
• Active substrate noise suppression in mixed-signal circuits using on-chip driven guard ringsWolfgang Winkler, Frank Herzel. 357-360 [doi]
• Impact of technology scaling on CMOS RF devices and circuitsEyad Abou-Allam, Tajinder Manku, Michele Ting, Michael S. Obrecht. 361-364 [doi]
• CMOS DLL based 2 V, 3.2 ps jitter, 1 GHz clock synthesizer and temperature compensated tunable oscillatorDavid J. Foley, Michael P. Flynn. 371-374 [doi]
• A 900 MHz, 2.5 mA CMOS frequency synthesizer with an automatic SC tuning loopTsung-Hsien Lin, William J. Kaiser. 375-378 [doi]
• A 2.5-Gb/s clock recovery circuit for NRZ data in 0.4-μm CMOS technologySeema Butala Anand, Behzad Razavi. 379-382 [doi]
• A 65 mW, 0.4-2.3 GHz bandpass filter for satellite receiversJohan van der Tang, Dieter Kasperkovitz, Arend Bretveld. 383-386 [doi]
• A 3 V linear input range tunable CMOS transconductor and its application to a 3.3 V 1.1 MHz Chebyshev low-pass Gm-C filter for ADSLJiunn-Yih Lee, Chien-Cheng Tu, Wei-Hong Chen. 387-390 [doi]
• m-C IF filter for BluetoothPietro Andreani, Sven Mattisson. 391-394 [doi]
• A CMOS readout circuit for pico-ampere thin film pyroelectric array detectorsTristan Reimann, Francois Krummenacher, B. Willing, P. Muralt, Michel J. Declercq. 395-398 [doi]
• Effect of technology scaling on digital CMOS logic stylesMohamed W. Allam, Mohab H. Anis, Mohamed I. Elmasry. 401-408 [doi]
• Boosted gate MOS (BGMOS): device/circuit cooperation scheme to achieve leakage-free giga-scale integrationTakashi Inukai, Makoto Takamiya, Kouichi Nose, Hiroshi Kawaguchi, Toshiro Hiramoto, Takayasu Sakurai. 409-412 [doi]
• th assignment and gate-sizingLiqiong Wei, Kaushik Roy 0001, Cheng-Kok Koh. 413-416 [doi]
• 5.5 V tolerant I/O in a 2.5 V 0.25 μm CMOS technologyAnne-Johan Annema, Govert Geelen, Peter C. de Jong. 417-420 [doi]
• Dynamic current mode logic (DyCML), a new low-power high-performance logic familyMohamed W. Allam, Mohamed I. Elmasry. 421-424 [doi]
• A noise-tolerant dynamic circuit design techniqueGanesh Balamurugan, Naresh R. Shanbhag. 425-428 [doi]
• Noise in mixers, oscillators, samplers, and logic an introduction to cyclostationary noiseJ. Phillips, Ken Kundert. 431-438 [doi]
• Complete noise analysis for CMOS switching mixers via stochastic differential equationsDonhee Ham, Ali Hajimiri. 439-442 [doi]
• Analysis of jitter due to power-supply noise in phase-locked loopsPayam Heydari, Massoud Pedram. 443-446 [doi]
• Nonlinear behavioral modeling and simulation of phase-locked and delay-locked systemsLin Wu, Huawen Jin, William C. Black Jr.. 447-450 [doi]
• Automated extraction of nonlinear circuit macromodelsJoel R. Phillips. 451-454 [doi]
• Finite-length signal quantization using discrete optimizationMark Chapman, Alper Demir 0001, Peter Feldmann. 455-458 [doi]
• A 4-tap 125-MHz mixed-signal echo canceller for Gigabit Ethernet on copper wireTai-Cheng Lee, Behzad Razavi. 461-464 [doi]
• A low complexity joint equalizer and decoder for 1000Base-T Gigabit EthernetErich F. Haratsch, Kamran Azadet. 465-468 [doi]
• A PN-acquisition ASIC for wireless CDMA systemsChristopher Deng, Charles Chien. 469-472 [doi]
• Media processor core architecture for realtime, bi-directional MPEG4/H.26X codec with 30 fr/s for CIF-videoT. Kamemaru, Hideo Ohira, H. Suzuki, K. Asano, Masahiko Yoshimoto, Tokumichi Murakami. 473-476 [doi]
• Efficient and reusable time-sharing architectures for equalizer structuresStefan R. Meier, Matthias Schoebinger. 477-480 [doi]
• A locally-clocked dynamic logic serial/parallel multiplierGregg N. Hoyer, Carl Sechen. 481-484 [doi]
• On-chip inductance modeling and RLC extraction of VLSI interconnects for circuit simulationXiaoning Qi, Gaofeng Wang, Zhiping Yu, Robert W. Dutton, Tak Young, Norman Chang. 487-490 [doi]
• Parasitic extraction for multimillion-transistor integrated circuits: methodology and design experienceEileen You, Swee Yav Choe, Chin Kim, Lakshminarasimh Varadadesikan, Kathirgamar Aingaran, John MacDonald. 491-494 [doi]
• Multi-aggressor relative window method for timing analysis including crosstalk delay degradationYasuhiko Sasaki, Kazuo Yano. 495-498 [doi]
• Multi-dimensional model reduction of VLSI interconnectsPavan K. Gunupudi, Michel S. Nakhla. 499-502 [doi]
• A novel high-performance predictable circuit architecture for the deep sub-micron eraYonghee Im, Kaushik Roy 0001. 503-506 [doi]
• Low power bus coding techniques considering inter-wire capacitancesPaul P. Sotiriadis, Anantha P. Chandrakasan. 507-510 [doi]
• WiCkeD: analog circuit synthesis incorporating mismatchKurt Antreich, Josef Eckmüller, Helmut Graeb, Michael Pronath, Frank Schenkel, Robert Schwencker, Stephan Zizala. 511-514 [doi]
• On intellectual property protectionEdoardo Charbon, Ilhami Torunoglu. 517-523 [doi]
• An analysis of the design processes required for the technology conversion of SoC intellectual propertyJames Nash, Philip Smith. 525-527 [doi]
• Firm IP development: methodology and deliverablesAdhikary Ranjit, Prakasam Ramkumar, Vargese Noel. 529-532 [doi]
• A new paradigm for very flexible SONET/SDH IP-modulesThomas Roewer, Manfred Stadler, Markus Thalmann, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner. 533-536 [doi]
• Merging hardware and software: intellectual property cores for Internet applicationsG. Bollano, S. Claretto, Enrica Filippi, A. Torielli, Maura Turolla. 537-540 [doi]
• VLSI implementation of a realtime wavelet video coderRoberto Yusi Omaki, Yu Dong, M. Horgan Miki, Makoto Furuie, Shohei Yamada, Daisuke Taki, Masaya Tarui, Gen Fujita, Takao Onoye, Isao Shirakawa. 543-546 [doi]
• A partitioned wavelet-based approach for image compression using FPGA'sJoerg Ritter 0002, Paul Molitor. 547-550 [doi]
• FLOVA: A four-issue VLIW geometry processor with SIMD instructions and lighting acceleration unitSang-Joon Nam, Byoung-Woon Kim, Yeon-Ho Im, Young-Su Kwon, Jun-Hee Lee, Young-Wook Cheon, Sung-Jae Byun, Dae-Hyun Lee, Chong-Min Kyung. 551-554 [doi]
• Novel VLIW code compaction method for a 3D geometry processorHiroaki Suzuki, Hiroshi Making, Yoshio Matsuda. 555-558 [doi]
• Multi-thread VLIW processor architecture for HDTV decodingHansoo Kim, Woo-Seung Yang, Myoung-Cheol Shin, Seung-Jai Min, Seong-Ok Bae, In-Cheol Park. 559-562 [doi]
• A full accuracy MPEG1 audio layer 3 (MP3) decoder with internal data convertersSekyoung Hong, Byungcheol Park, Yoonseok Song, Hangyo See, Jonghyun Kim, Hyungjong Lee, Dalsoo Kim, Minkyu Song. 563-566 [doi]
• Physical processes of phase noise in differential LC oscillatorsJacob J. Rael, Asad A. Abidi. 569-572 [doi]
• A new approach to fully integrated CMOS LC-oscillators with a very large tuning rangeFrank Herzel, Heide Erzgraeber, Nikolay Ilkov. 573-576 [doi]
• A 1 mA, -120.5 dbc/Hz at 600 kHz from 1.9 GHz fully tuneable LC CMOS VCOFrancesco Svelto, Stefano Deantoni, Rinaldo Castello. 577-580 [doi]
• A 10 GHz CMOS distributed voltage controlled oscillatorHui Wu, Ali Hajimiri. 581-584 [doi]
• A 1.8 GHz highly-tunable low-phase-noise CMOS VCOBram De Muer, Nobuyulu Itoh, Marc Borremans 0001, Michiel Steyaert. 585-588 [doi]
• A fully-integrated low phase-noise nested-loop PLL for frequency synthesisAmr N. Hafez, Mohamed I. Elmasry. 589-592 [doi]
• A low power high spectral purity frequency translational loop for wireless applicationsMihai A. Margarit, M. Jamal Deen. 593-596 [doi]