Koichi Takeda 0001 - researchr alias

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Viewing Publication 1 - 6 from 6

2006

A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applicationsKoichi Takeda 0001, Yasuhiko Hagihara, Yoshiharu Aimoto, Masahiro Nomura, Yoetsu Nakazawa, Toshio Ishii, Hiroyuki Kobatake. jssc, 41(1):113-121, 2006. [doi]

Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modesMasahiro Nomura, Yoshifumi Ikenaga, Koichi Takeda 0001, Yoetsu Nakazawa, Yoshiharu Aimoto, Yasuhiko Hagihara. jssc, 41(4):805-814, 2006. [doi]

2001

An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shieldKenji Noda, Koichi Takeda 0001, Koujirou Matsui, Shinya Ito, Sadaaki Masuoka, Hideaki Kawamoto, Nobuyuki Ikezawa, Yoshiharu Aimoto, Noritsugu Nakamura, Takahiro Iwasaki, Hideo Toyoshima, Tadahiko Horiuchi. jssc, 36(3):510-515, 2001. [doi]

2000

1996

A 6-ns, 1.5-V, 4-Mb BiCMOS SRAMHideo Toyoshima, Shigeru Kuhara, Koichi Takeda 0001, Kazuyuki Nakamura, Hiloshi Okamura, Masahide Takada, Hisamitsu Suzuki, Hiroshi Yoshida, Tohru Yamazaki. jssc, 31(11):1610-1617, 1996. [doi]

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