Yasuhiko Hagihara - researchr alias

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Viewing Publication 1 - 12 from 12

2019

2016

2015

2008

A Circuit for Determining the Optimal Supply Voltage to Minimize Energy Consumption in LSI Circuit OperationsYoshifumi Ikenaga, Masahiro Nomura, Yoetsu Nakazawa, Yasuhiko Hagihara. jssc, 43(4):911-918, 2008. [doi]

2006

A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applicationsKoichi Takeda 0001, Yasuhiko Hagihara, Yoshiharu Aimoto, Masahiro Nomura, Yoetsu Nakazawa, Toshio Ishii, Hiroyuki Kobatake. jssc, 41(1):113-121, 2006. [doi]

Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modesMasahiro Nomura, Yoshifumi Ikenaga, Koichi Takeda 0001, Yoetsu Nakazawa, Yoshiharu Aimoto, Yasuhiko Hagihara. jssc, 41(4):805-814, 2006. [doi]

An Automatic Bi-Directional Bus Repeater Control Scheme Using Dynamic Collaborative Driving TechniquesMasahiro Nomura, Taku Ohsawa, Koichi Takeda, Yoetsu Nakazawa, Yoshinori Hirota, Yasuhiko Hagihara, Naoki Nishi. ieicet, 89-C(3):334-341, 2006. [doi]

Domino Logic Synthesis System and its ApplicationsKo Yoshikawa, Shigeto Inui, Yasuhiko Hagihara, Yuichi Nakamura, Takeshi Yoshimura. jcsc, 15(2):277-287, 2006. [doi]

2004

Timing optimization by replacing flip-flops to latchesKo Yoshikawa, Yasuhiko Hagihara, Keisuke Kanamaru, Yuichi Nakamura, Shigeto Inui, Takeshi Yoshimura. aspdac 2004: 186-191 [doi]

1997

Floating-point datapaths with online built-in self speed testYasuhiko Hagihara, Shigeto Inui, Fuyuki Okamoto, Masato Nishida, Toshihiko Nakamura, Hachiro Yamada. jssc, 32(3):444-449, 1997. [doi]

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