Kunihiko Iizuka - researchr alias

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Viewing Publication 1 - 25 from 25

2016

2015

A 24-bit multi-functional sensor analog front end employing low noise biasing technique with 8.2nV/√Hz input referred noiseMasahiko Maruyama, Shigenari Taguchi, Masafumi Yamanoue, Kunihiko Iizuka. asscc 2015: 1-4 [doi]

97-mW 8-Phase CMOS VCO and Dividers for a 134-GHz PLL SynthesizerTakeshi Mitsunaka, Kunihiko Iizuka, Minoru Fujishima. ieicet, 98-C(7):685-692, 2015. [doi]

2014

8-GHz Locking Range and 0.4-pJ Low-Energy Differential Dual-Modulus 10/11 PrescalerTakeshi Mitsunaka, Masafumi Yamanoue, Kunihiko Iizuka, Minoru Fujishima. ieicet, 97-C(6):486-494, 2014. [doi]

9dB NF and +11dBm OIP3 CMOS Single Conversion Front-End for a Satellite Low-Noise Block Down-ConverterTakeshi Mitsunaka, Yusuke Kishino, Masafumi Yamanoue, Kunihiko Iizuka, Minoru Fujishima. ieicet, 97-A(1):101-108, 2014. [doi]

2011

Capacitively Coupled Non-Contact Probing Circuits for Membrane-Based Wafer-Level Simultaneous TestingMutsuo Daito, Yoshiro Nakata, Satoshi Sasaki, Hiroyuki Gomyo, Hideki Kusamitsu, Yoshio Komoto, Kunihiko Iizuka, Katsuyuki Ikeuchi, Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai. jssc, 46(10):2386-2395, 2011. [doi]

2010

Capacitively coupled non-contact probing circuits for membrane-based wafer-level simultaneous testingMutsuo Daito, Yoshiro Nakata, Satoshi Sasaki, Hiroyuki Gomyo, Hideki Kusamitsu, Yoshio Komoto, Kunihiko Iizuka, Katsuyuki Ikeuchi, Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai. isscc 2010: 144-145 [doi]

ForewordKunihiko Iizuka. ieicet, 93-C(6):717, 2010. [doi]

2009

A 100 MS/s 4 MHz Bandwidth 70 dB SNR ΔΣ ADC in 90 nm CMOSYoshihisa Fujimoto, Yusuke Kanazawa, Pascal Lo Ré, Kunihiko Iizuka. jssc, 44(6):1697-1708, 2009. [doi]

2008

RF Variable-Gain Amplifiers and AGC Loops for Digital TV ReceiversKunihiko Iizuka, Masato Koutani, Takeshi Mitsunaka, Hiroshi Kawamura, Shinji Toyoyama, Masayuki Miyamoto, Akira Matsuzawa. ieicet, 91-C(6):854-861, 2008. [doi]

2007

A 184 mW Fully Integrated DVB-H Tuner With a Linearized Variable Gain LNA and Quadrature Mixers Using Cross-Coupled TransconductorKunihiko Iizuka, Hiroshi Kawamura, Takanobu Fujiwara, Kanetomo Kagoshima, Shuichi Kawama, Hiroshi Kijima, Masato Koutani, Shinji Toyoyama, Keiichi Sakuno. jssc, 42(4):862-871, 2007. [doi]

A Digitally Controlled Variable-Gain Low-Noise Amplifier With Strong Immunity to InterferersMasato Koutani, Hiroshi Kawamura, Shinji Toyoyama, Kunihiko Iizuka. jssc, 42(11):2395-2403, 2007. [doi]

2006

2005

A high OIP3 quadrature mixer using cross-coupled transconductorMasato Koutani, Kunihiko Iizuka. cicc 2005: 345-348 [doi]

2002

Embedded anti-aliasing in switched-capacitor ladder filters with variable gain and offset compensationShin'ichiro Azuma, Shuichi Kawama, Kunihiko Iizuka, Masayuki Miyamoto, Daniel Senderowicz. jssc, 37(3):349-356, 2002. [doi]

2001

2000

A 2-V 3.7-mW delay locked-loop using recycling integrator correlators for a 5-Mcps DS-CDMA demodulatorYoshihisa Fujimoto, Shuichi Kawama, Kunihiko Iizuka, Masayuki Miyamoto, Daniel Senderowicz. cicc 2000: 35-38 [doi]

1999

A parallel analog intelligent vision sensor with a variable receptive fieldTetsuya Yagi, Seiji Kameda, Kunihiko Iizuka. scjapan, 30(1):60-69, 1999. [doi]

1996

Dynamically Adaptable CMOS Winner-Take-All Neural NetworkKunihiko Iizuka, Masayuki Miyamoto, Hirofumi Matsui. nips 1997: 713-719 [doi]

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