A 14-bit digitally self-calibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40 MS/s - researchr publication

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Kunihiko Iizuka, Hirofumi Matsui, Masaya Ueda, Mutsuo Daito. A 14-bit digitally self-calibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40 MS/s. J. Solid-State Circuits, 41(4):883-890, 2006. [doi]

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