A 14-bit digitally self-calibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40 MS/s

Kunihiko Iizuka, Hirofumi Matsui, Masaya Ueda, Mutsuo Daito. A 14-bit digitally self-calibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40 MS/s. J. Solid-State Circuits, 41(4):883-890, 2006. [doi]

@article{IizukaMUD06,
  title = {A 14-bit digitally self-calibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40 MS/s},
  author = {Kunihiko Iizuka and Hirofumi Matsui and Masaya Ueda and Mutsuo Daito},
  year = {2006},
  doi = {10.1109/JSSC.2006.870788},
  url = {https://doi.org/10.1109/JSSC.2006.870788},
  researchr = {https://researchr.org/publication/IizukaMUD06},
  cites = {0},
  citedby = {0},
  journal = {J. Solid-State Circuits},
  volume = {41},
  number = {4},
  pages = {883-890},
}