Table of Contents

• Welcome and opening remarksTrudy Stetzler. 1 [doi]
• Body wellness without wiresJim Lipman, Albert Wang. 2-3 [doi]
• Wirelessly powered and bidirectional data exchanged in smart medical microsystemsMohamad Sawan, Yamu Hu, Jonathan Coulombe. 5-12 [doi]
• Human++: autonomous wireless sensors for body area networksBert Gyselinckx, Chris Van Hoof, Julien Ryckaert, Refet Firat Yazicioglu, Paolo Fiorini, Vladimir Leonov. 13-19 [doi]
• Noise and reliability containment approachesGordon W. Roberts, Robert C. Aitken. 20-21 [doi]
• Robust platform design in advanced VLSI technologiesDavid J. Leavins, Kee Sup Kim, Subhasish Mitra, Eddie J. Rodriguez. 23-30 [doi]
• An integrated timing and dynamic supply noise verification for nano-meter CMOS SoC designsKenji Shimazaki, Mitsuya Fukazawa, Makoto Nagata, Shingo Miyahara, Masaaki Hirata, Kazuhiro Satoh, Hiroyuki Tsujikawa. 31-34 [doi]
• Substrate-noise and random-fluctuations reduction with self-adjusted forward body biasYoshihide Komatsu, Koichiro Ishibashi, Masaharu Yamamoto, Toshiro Tsukada, Kenji Shimazaki, Mitsuya Fukazawa, Makoto Nagata. 35-38 [doi]
• Auto-referenced on-die power supply noise measurement circuitChaiyuth Chansungsan. 39-42 [doi]
• Real-world SoC design methods and applicationsThomas Zimmermann, Aurangzeb Khan. 42-43 [doi]
• The design methodology and implementation of a first-generation CELL processor: a multi-core SoCDac Pham, Erwin Behnen, Mark Bolliger, H. Peter Hofstee, Charles R. Johns, James A. Kahle, Atsushi Kameyama, John M. Keaty, Bob Le, Yoshio Masubuchi, Stephen D. Posluszny, Mack W. Riley, Masakazu Suzuoki, Michael Wang, James D. Warnock, Steve Weitzel, Dieter F. Wendel, Kazuaki Yazawa. 45-49 [doi]
• Scalable bus interface for HSDPA co-processor extensionToshiki Takeuchi, Hiroyuki Igura, Takeshi Hashimoto, Soichi Tsumura, Naoki Nishi. 51-54 [doi]
• A low-power mixed-signal baseband system design for wireless sensor networksYanmei Li, Fernando De Bernardinis, Brian P. Otis, Jan M. Rabaey, Alberto L. Sangiovanni-Vincentelli. 55-58 [doi]
• A 64 channel programmable receiver chip for 3G wireless infrastructureS. Sriram, Kathy Brown, Raphael Defosseux, Filip Moerman, Olivier Paviot, V. Sundararajan, Alan Gatherer. 59-62 [doi]
• A heterogeneous functional verification platformAmir Hekmatpour, Charles Alley, Brian Stempel, James Coulter, Azadeh Salehi, Arash Shafie, Chloe Palenchar. 63-66 [doi]
• DSP for wirelessLawrence Clark, Masataka Matsui. 66-67 [doi]
• A low-power ASIC implementation of 2Mbps antenna-rake combiner for WCDMA with MRC and LMS capabilitiesAlireza Tarighat, Eugene Grayver, Ahmed M. Eltawil, Jean-François Frigon, Gennady Y. Poberezhskiy, Hanli Zou, Babak Daneshrad. 69-72 [doi]
• Implementation of a digital timing recovery circuit for CDMA applicationsAhmed M. Eltawil, Eugene Grayver, Alireza Tarighat, Jean-François Frigon, Aliazam Abbasfar. 73-76 [doi]
• A low-area decimation filter for ultra-high speed 1-bit ΣΔ A/D convertersKhurram Muhammad, Imtinan Elahi, Tom Jung. 77-80 [doi]
• A digital 120Mb/s MIMO-OFDM baseband processor for high speed wireless LANsYunho Jung, Jiho Kim, Seungphyo Noh, Hongil Yoon, Jaeseok Kim. 81-84 [doi]
• Emerging technologies for unique applicationsAnn Marie Rincon, Kris Iniewski. 84-85 [doi]
• Integration of self assembly for semiconductor microelectronicsCharles T. Black. 87-91 [doi]
• 2 integrated capacitive vibration sensor with sub-10 zF/rt-Hz noise floorSitaraman V. Iyer, Hasnain Lakdawala, Rajarishi S. Sinha, Eric J. Zacherl, Richard T. Unetich, Daniel M. Gaugel, David F. Guillou, L. Richard Carley. 93-96 [doi]
• Electric power generation using piezoelectric resonator for power-free sensor nodeHidetoshi Tanaka, Goichi Ono, Tomohiro Nagano, Norio Ohkubo. 97-100 [doi]
• A 0.14mW/Gbps high-density capacitive interface for 3D system integrationAlberto Fazzi, Luca Magagni, Mauro Mirandola, Roberto Canegallo, Stefan Schmitz, Roberto Guerrieri. 101-104 [doi]
• Initialization of a wireless clock distribution system using an external antennaRan Li, Xiaoling Guo, Dong-Jun Yang, Kenneth K. O. 105-108 [doi]
• Circuits and systems for high-speed linksAmjad Obeidat, Eric Naviasky. 108-109 [doi]
• Algorithmic design methodologies and design porting of wireline transceiver IC building blocks between technology nodesSorin P. Voinigescu, Timothy O. Dickson, Theodoros Chalvatzis, Altan Hazneci, Ekaterina Laskin, Rudy Beerkens, Imran Khalid, Edward S. Rogers Sr.. 111-118 [doi]
• A 45.6-GHz matrix distributed amplifier in 0.18-nm CMOSTai-Yuan Chen, Jun-Chau Chien, Liang-Hung Lu. 119-122 [doi]
• A 3V, 4.25Gb/s laser driver with 0.4V output voltage complianceJohn W. Fattaruso, Benjamin Sheahan. 123-126 [doi]
• Notice of Violation of IEEE Publication PrinciplesA 10.7GHz SiGe BICMOS limiting amplifier using multiple offset cancellation loopsAdrian Maxim. 127-130 [doi]
• A 0.8-1.3V 16-channel 2.5Gb/s high-speed serial transceiver in a 90nm standard CMOS processYoshiyasu Doi, Syunitirou Masaki, Takaya Chiba, Hirohito Higashi, Hisakatsu Yamaguchi, Hideki Takauchi, Hideki Ishida, Kohtaroh Gotoh, Junji Ogawa, Hirotaka Tamura. 131-134 [doi]
• An integrated CMOS transceiver for a 40Gb/s SCM optical communication systemJinghong Chen, Fadi Saibi, Eduard Säckinger, Kamran Azadet, Joe Othmer, Mark Yu, Fuji Yang, Jenshan Lin, Titus Huang, Tingping Liu. 135-138 [doi]
• Ultra wideband circuits and transceiversRanjit Gharpurey, Stefan Drude. 138-139 [doi]
• Multiband UWB transceiversBehzad Razavi, Turgut Aytur, Christopher Lam, Fei-Ran Yang, Ran-Hong Yan, Han-Chang Kang, Cheng-Chung Hsu, Chao-Cheng Lee. 141-148 [doi]
• A low power implementation for the transmit path of a UWB transceiverSudhir Aggarwal, Domine Leenaerts, Remco van de Beek, Gerard Van der Weide, Harish Kundur, Jos Bergervoet, A. Landesman, Yifeng Zhang, Charles J. Razzell, Helen Waite, Raf Roovers. 149-152 [doi]
• A BiCMOS ultra-wideband 3.1-10.6GHz front-endFred S. Lee, Anantha Chandrakasan. 153-156 [doi]
• An interference robust 0.18μm CMOS 3.1-8GHz receiver front-end for UWB radioGiuseppe Cusmai, Massimo Brandolini, Paolo Rossi, Francesco Svelto. 157-160 [doi]
• A broadband noise-canceling CMOS LNA for 3.1-10.6-GHz UWB receiverChih-Fan Liao, Shen-Iuan Liu. 161-164 [doi]
• A 90-nm MOS-only 3-11GHz transmitter for UWBYorgos Palaskas, Ralph E. Bishop, Ashoke Ravi, Krishnamurthy Soumyanath. 165-168 [doi]
• Advances in programmable logicSteven J. E. Wilton, Albert Stritter. 168-169 [doi]
• Two-stage physical synthesis for FPGAsDeshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown. 171-178 [doi]
• An improved "soft" eFPGA design and implementation strategyVictor Aken Ova, Guy Lemieux, Resve Saleh. 179-182 [doi]
• Heterogeneous routing architecture for low-power FPGA fabricArifur Rahman, Satyaki Das, Tim Tuan, Anirban Rahut. 183-186 [doi]
• Look-up table leakage reduction for FPGAsNavid Azizi, Farid N. Najm. 187-190 [doi]
• A continuous-time hierarchical field programmable analogue arrayDavid Varghese, J. Neil Ross. 191-194 [doi]
• Poster sessionLarry Wissel. 194-195 [doi]
• A 1.2V, 10MHz, low-pass Gm-C filter with Gm-cells based on triode-biased MOS and passive resistor in 0.13μm CMOS technologyJun-Gi Jo, Changsik Yoo, Chun-Seok Jeong, Chan-Young Jeong, Mi-Young Lee, Jong-Kee Kwon. 195-198 [doi]
• Spark current in charge pump of phase lock loopKai Di Feng, Jui-Chu Lee. 199-202 [doi]
• A 47.3-MHz SAW resonator based CMOS second-order bandpass sigma-delta modulator with 54-dB peak SNDRRui Yu, Yong Ping Xu. 203-206 [doi]
• A high current driving charge pump with current regulation methodSoon-Kyun Shin, Bai-Sun Kong, Chil-Gee Lee, Young-Hyun Jun, Jae-Whui Kim. 207-210 [doi]
• On-chip temperature control circuit using common devicesFrancis D. Braun, David W. Parent, Tamara A. Papalias. 215-218 [doi]
• Reducing power in flexible a-Si digital circuits while preserving stateKyle R. Wissmiller, Jonathan E. Knudsen, Travis J. Alward, Zi P. Li, David R. Allee, Lawrence T. Clark. 219-222 [doi]
• An 8/4-bit reconfigurable digital pixel array with on-chip non-uniform quantizerAmine Bermak. 223-226 [doi]
• A high performance, high voltage output buffer in a low voltage CMOS processRajat Chauhan, Karthik Rajagopal, Vinod Menezes, H. M. Roopashree, Sanish Koshy Jacob. 227-230 [doi]
• A slew rate-controlled output driver having a constant transition time over the variations of process, voltage and temperatureSoon-Kyun Shin, Wang Yu, Bai-Sun Kong, Chil-Gee Lee, Young-Hyun Jun, Jae-Whui Kim. 231-234 [doi]
• Fine-grained power managed dual-thread vector scalar unit for the first-generation CELL processorTom Beacom, Timothy C. Buchholtz, D. Bradley, Jack Randolph, Salvatore N. Storino, Mark Veldhuizen, Sherman M. Dance, Jente B. Kuang, Steve Schwinn, Sue Cox, Fred Ziegler, J. Kao, Chuck Li, Christophe Tretz, J. Cabellon, Andrew Freemyer, Matthew Tubbs. 235-238 [doi]
• Eliminating memory bottlenecks for a JPEG encoder through distributed logic-memory architecture and computation-unit integrated memoryChao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. 239-242 [doi]
• An 80-Mb/s 0.18-μm CMOS analog min-sum iterative decoder for a (32, 8, 10) LDPC codeSaied Hemati, Amir H. Banihashemi, Calvin Plett. 243-246 [doi]
• XDXMOS: a novel technique for the double-gate MOSFETs logic circuits - to achieve high drive current and small input capacitance togetherHanpei Koike, Toshihiro Sekigawa. 247-250 [doi]
• Design and characterization of a MEMS capacitive switch for improved RF amplifier circuitsJohn Danson, Calvin Plett, Niall Tait. 251-254 [doi]
• An embedded nonvolatile FRAM with electrical fuse repair scheme and one time programming scheme for high performance smart cardsByungJun Min, Kang-Woon Lee, Han-Ju Lee, So-Ra Kim, Seung-Gyu Oh, Byung-gil Jeon, Hee-Hyun Yang, Min-Kyu Kim, Sung Hee Cho, Honsik Cheong, Chilhee Chung, Kinam Kim. 255-258 [doi]
• A 333MHz random cycle DRAM using the floating body cellKosuke Hatsuda, Katsuyuki Fujita, Takashi Ohsawa. 259-262 [doi]
• A one time programming cell using more than two resistance levels of a polyfuseJohannes Fellner. 263-266 [doi]
• An overview of structured digital ASIC XPressArray/spl reg/-II I/OTroy Ruud, Zhongmin Li, Rich Friel, Bryce Rasmussen, Shan Mo. 267-270 [doi]
• An implemented of H.264 video decoder using hardware and softwareSeongMo Park, Hanjin Cho, Heebum Jung, Dukdong Lee. 271-275 [doi]
• Dynamically reconfigurable NoC for reconfigurable MPSoCBalal Ahmad, Tughrul Arslan. 277-280 [doi]
• Efficient analytical modeling techniques for rapid integrated spiral inductor prototypingArthur Nieuwoudt, Michael S. McCorquodale, Ruba T. Borno, Yehia Massoud. 281-284 [doi]
• Miniaturized 3-dimensional transformer designWei-Zen Chen, Kuo-Ching Hsu. 285-288 [doi]
• Generalized method of the time-domain circuit simulation based on LIM with MNA formulationHidemasa Kubota, Yuichi Tanji, Takayuki Watanabe, Hideki Asai. 289-292 [doi]
• Generalized noise analysis of active mixers by simple linear periodic time-varying circuit modelJongrit Lerdworatawee, Won Namgoong. 293-296 [doi]
• Behavioral test benches for digital clock and data recovery circuits using Verilog-AS. I. Ahmed, Kent Orthner, Tadeusz Kwasniewski. 297-300 [doi]
• The importance of including thermal effects in estimating the effectiveness of power reduction techniquesJa Chun Ku, Maged Ghoneima, Yehea I. Ismail. 301-304 [doi]
• Measurement and analysis of delay variation due to inductive couplingYasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye. 305-308 [doi]
• Simulation and analysis of inductive impact on VLSI interconnects in the presence of process variationsXiaoning Qi, Sam C. Lo, Yansheng Luo, Alex Gyure, Mahmoud Shahram, Kishore Singhal. 309-312 [doi]
• Low-power prediction based data transfer architectureMaged Ghoneima, Ehsan Atoofian, Amirali Baniasadi, Yehea I. Ismail. 313-316 [doi]
• Design considerations for 2nd-order and 3rd-order bang-bang CDR loopsShoujun Wang, HaiTao Mei, Mashkoor Baig, William Bereza, Tadeusz Kwasniewski, Rakesh H. Patel. 317-320 [doi]
• A monolithic vernier-based time-to-digital converter with dual PLLs for self-calibrationPoki Chen, Jia-Chi Zheng, Chun-Chi Chen. 321-324 [doi]
• A 500MHz DLL with second order duty cycle corrector for low jitterByung-Guk Kim, Kwang-Il Oh, Lee-Sup Kim, Dae Woo Lee. 325-328 [doi]
• Fractional-N PLL with 90/spl deg/ phase shift lock and active switched-capacitor loop filterJoohwan Park, Franco Maloberti. 329-332 [doi]
• 10 Gb/s CMOS laser driver with 3.3 V/sub pp/ output swingDay-Uei Li, Li-Ren Huang, Chia-Ming Tsai. 333-336 [doi]
• A performance optimized CMOS distributed LNA for UWB receiversPayam Heydari, Denis Lin. 337-340 [doi]
• Robust multi-GHz (7.4GHz) on-chip image rejection in CMOSRola A. Baki, Mourad N. El-Gamal. 341-344 [doi]
• A high OIP3 quadrature mixer using cross-coupled transconductorMasato Koutani, Kunihiko Iizuka. 345-348 [doi]
• A Integrated Dual Direct-Conversion Tuner Chip for Digital Satellite ApplicationWeinan Gao, Kendal Hess, Ray Rosik, Mark Santini, Mats Lindstrom, Jason McFee, Jacek Czajka. 346-349 [doi]
• A GSM receiver front-end in 65 nm digital CMOS processSee Taur Lee, Solti Peng. 349-352 [doi]
• A new receiver architecture for multiple-antenna systemsHamid Rafati, Behzad Razavi. 357-360 [doi]
• A 3.6mW 2.4-GHz multi-channel super-regenerative receiver in 130nm CMOSJia-yi Chen, Michael P. Flynn, John P. Hayes. 361-364 [doi]
• Low-power and high-linearity mixer design using complex transconductance equivalent circuitWei-Chia Zhan, Chien-Nan Kuo, Jyh-Chyurn Guo. 365-368 [doi]
• Data convertersKathleen Philips, David G. Nairn. 366-367 [doi]
• Using cache to reduce power in content-addressable memories (CAMs)Kostas Pagiamtzis, Ali Sheikholeslami. 369-372 [doi]
• Scaling of analog-to-digital converters into ultra-deep-submicron CMOSYun Chiu, Borivoje Nikolic, Paul R. Gray. 375-382 [doi]
• A /spl Delta//spl Sigma/ DAC with reduced activity data weighted averaging and anti-jitter digital filterAra Bicakci, Gurjinder Singh. 383-386 [doi]
• A 10.24GSPS photonic sampled bandpass /spl Delta//spl Sigma/ modulator direct-sampling at 12GHzLouis Luh, Willie Ng, Joseph F. Jensen, Duc Le, David L. Persechini, Stephen Thomas, Charles H. Fields, James Lin. 387-390 [doi]
• A 14-bit 125 MS/s IF/RF sampling pipelined A/D converterAhmed M. A. Ali, Christopher Dillon, Robert Sneed, Andrew Morgan, John Kornblum, Lu Wu, Scott Bardsley. 391-394 [doi]
• A 1.0 V 40mW 10b 100MS/s pipeline ADC in 90nm CMOSHirotomo Ishii, Ken Tanabe, Tetsuya Iida. 395-398 [doi]
• A 50 MS/s 12-bit CMOS pipeline A/D converter with nonlinear background calibrationJie Yuan, Nabil H. Farhat, Jan Van der Spiegel. 399-402 [doi]
• High-speed wave-shaping techniquesShahriar Mirabbasi, Cormac O'Connell. 400-401 [doi]
• Dual scalable 500MS/s, 5b time-interleaved SAR ADCs for UWB applicationsBrian P. Ginsburg, Anantha P. Chandrakasan. 403-406 [doi]
• Crosstalk-induced jitter equalizationJames Buckwalter, Ali Hajimiri. 409-412 [doi]
• A continuous-time adaptive FIR equalizer with LNV-AIL delay line for 2.5Gb/s data communicationXiaofeng Lin, Hoi Lee, Jin Liu. 413-416 [doi]
• Memory circuits and technologyTakashi Akioka, Jean-Christophe Vial. 414-415 [doi]
• A 40 Gb/s transversal filter in 0.18 /spl mu/m CMOS using distributed amplifiersJonathan Sewter, Anthony Chan Carusone. 417-420 [doi]
• Emerging memory technologiesKinam Kim, Gitae Jeong, Hong-Sik Jeong, Sungyung Lee. 423-426 [doi]
• An 8Mb 1T1C ferroelectric memory with zero cancellation and micro-granularity redundancyJarrod Eliason, Sudhir Madan, Hugh P. McAdams, Glen Fox, Ted Moise, Changgui Lin, Kurt Schwartz, Jim Gallia, Edwin Jabillo, Bill Kraus, Scott R. Summerfelt. 427-430 [doi]
• Phase change RAM operated with 1.5-V CMOS as low cost embedded memoryKenichi Osada, Takayuki Kawahara, Riichiro Takemura, Naoki Kitai, Norikatsu Takaura, Nozomu Matsuzaki, Kenzo Kurotsuchi, Hiroshi Moriya, Masahiro Moniwa. 431-434 [doi]
• A capacitorless twin-transistor random access memory (TTRAM) on SOIFukashi Morishita, Hideyuki Noda, Takayuki Gyohten, Mako Okamoto, Takashi Ipposhi, Shigeto Maegawa, Katsumi Dosaka, Kazutami Arimoto. 435-438 [doi]
• Fast and accurate estimation of nano-scaled SRAM read failure probability using critical point samplingIk Joon Chang, Kunhyuk Kang, Saibal Mukhopadhyay, Chris H. Kim, Kaushik Roy. 439-442 [doi]
• Programmable techniques for cell stability test and debug in embedded SRAMsAndrei Pavlov, Manoj Sachdev, José Pineda de Gyvez, Mohamed Azimane. 443-446 [doi]
• Low-noise embedded CAM with reduced slew-rate match-lines and asynchronous search-linesIgor Arsovski, Rahul Nadkarni. 447-450 [doi]
• Substrate and phase noise characterizationSteffen Rochel, Hidetoshi Onodera. 448-449 [doi]
• A soft-error-immune maintenance-free TCAM architecture with associated embedded DRAMHideyuki Noda, Katsumi Dosaka, Fukashi Morishita, Kazutami Arimoto. 451-454 [doi]
• Phase noise in inverter-based & differential CMOS ring oscillatorsAsad A. Abidi, Sohrab Samadian. 457-460 [doi]
• oder: http: //potol.eecs.berkeley.edu/~jr Analytical equations for predicting injection locking in LC and ring oscillatorsXiaolue Lai, Jaijeet Roychowdhury. 461-464 [doi]
• A multiple-probe approach for robust frequency domain ring oscillator simulationXiaochun Duan, Kartikeya Mayaram. 465-468 [doi]
• Synthesized compact model and experimental results for substrate noise coupling in lightly doped processesHai Lan, Tze Wee Chen, Chi On Chui, Parastoo Nikaeen, Jae Wook Kim, Robert W. Dutton. 469-472 [doi]
• Substrate noise analysis and experimental verification for the efficient noise prediction of a digital PLLNisha Checka, Anantha P. Chandrakasan, Rafael Reif. 473-476 [doi]
• ESD implementation strategiesMike Zachariah, Robert C. Aitken. 474-475 [doi]
• Substrate noise immune design of an LC-tank VCO using sensitivity functionsCharlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay. 477-480 [doi]
• Advanced SCR ESD protection circuits for CMOS/SOI nanotechnologiesMarkus P. J. Mergens, Olivier Marichal, Steven Thijs, Benjamin Van Camp, Christian C. Russ. 481-488 [doi]
• RF ESD protection strategies - the design and performance trade-off challengesPhilippe Jansen, Steven Thijs, Dimitri Linten, M. I. Natarajan, Vesselin K. Vassilev, Mingxu Liu, Ann Concannon, David Trémouilles, Takeshi Nakaie, Masanori Sawada, Vladislav A. Vashchenko, Marcel ter Beek, Takumi Hasebe, Stefaan Decoutere, Guido Groeseneken. 489-496 [doi]
• Custom circuitsJamil Kawa, Jackie Snyder. 496-497 [doi]
• Low-power low-noise highly ESD robust LNA, and VCO design using above-IC inductorsDimitri Linten, Xiao Sun, Steven Thijs, M. I. Natarajan, Abdelkarim Mercha, Geert Carchon, Piet Wambacq, Takeshi Nakaie, Stefaan Decoutere. 497-500 [doi]
• Differential ring oscillators with multipath delay stagesSrikanth S. Mohan, W. S. Chan, David M. Colleran, S. F. Greenwood, J. E. Gamble, I. G. Kouznetsov. 503-506 [doi]
• A high throughput divider implementationXinyu Guo, Carl Sechen. 507-510 [doi]
• Piezoresistive CMOS-MEMS pressure sensor with ring oscillator readout including Δ-Σ analog-to-digital converter on-chipKarianne Oysted, Dag T. Wisland. 511-514 [doi]
• A highly-integrated CMOS analog baseband transceiver with 180MSPS 13b pipelined CMOS ADC and dual 12b DACsKush Gulati, Mark Peng, Anurag Pulincherry, Carlos E. Muñoz, Mike Lugin, Alex R. Bugeja, Jipeng Li, Anantha P. Chandrakasan. 515-518 [doi]
• A 1.2Gb/s write driver with pre-emphasis overshoot control optimized for high density HDD applicationsY. Hayashi, Masahito Sonehara, S. Ueno, Y. Ito, Akio Koyama, Hiroki Yamashita. 519-522 [doi]
• A 9.2mW 528/66/50MHz monolithic clock synthesizer for mobile μP platformsMichael S. McCorquodale, Scott M. Pernia, Justin D. O'Day, Gordy A. Carichner, Sundus Kubba. 523-526 [doi]
• Clocking circuits for wireline communicationsJafar Savoj, Ramesh Harjani. 526-527 [doi]
• A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSIMototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Chen Kong Teh, Takayoshi Shimazawa, Naoyuki Kawabe, Takeshi Kitahara, Yu Kikuchi, Tsuyoshi Nishikawa, Makoto Takahashi, Yukihito Oowaki. 527-530 [doi]
• Low voltage wide range DLL-based quad-phase core clock generator for high speed network SRAM applicationNam-Seog Kim, Uk-Rae Cho, Hyun-Geun Byun. 533-536 [doi]
• A digital clock and data recovery architecture for multi-gigabit/s binary linksJeff L. Sonntag, John T. Stonick. 537-544 [doi]
• Notice of Violation of IEEE Publication Principles9.953-12.5GHz 0.13μm CMOS LC VCO using a high resolution calibration and a constant gain varactorAdrian Maxim, C. Turinici. 545-548 [doi]
• An improved wideband PLL with adaptive frequency response that tracks the referenceMike Hufford, Eric Naviasky, Stephen Williams, Michelle Williams. 549-552 [doi]
• T SiGe processJing-Hong Conan Zhan, Jon S. Duster, Kevin T. Kornegay. 552-555 [doi]
• A versatile low-jitter PLL in 90-nm CMOS for SerDes transmitter clockingAlvin Leng Sun Loke, Robert K. Barnes, Tin Tin Wee, Michael M. Oshima, Charles E. Moore, Ronald R. Kennedy, Jim O. Barnes, Robert A. Zimmer, Kari L. Arave, H. Herman M. Pang, Tom E. Cynkar, Aaron M. Volz, Jim R. Pfiester, R. J. Martin, Robert H. Miller, David A. Hood, Gordon W. Motley, Ed J. Rojas, Tom M. Walley, Michael J. Gilsdorf. 553-556 [doi]
• Silicon millimeter wave ICs, VCOs, and dividersKevin T. Kornegay, N. Itoh. 556-557 [doi]
• Progress toward a low-cost millimeter-wave silicon radioScott K. Reynolds, Brian A. Floyd, Ullrich R. Pfeiffer, Troy J. Beukema, Thomas Zwick, Janus Grzyb, Duixian Liu, Brian P. Gaucher. 563-570 [doi]
• A wideband 77GHz, 17.5dBm power amplifier in siliconAbbas Komijani, Ali Hajimiri. 571-574 [doi]
• Balanced CMOS LC-tank analog frequency dividers for quadrature LO generationAndrea Mazzanti, Luca Larcher, Francesco Svelto. 575-578 [doi]
• A tail current-shaping technique to reduce phase noise in LC VCOsBaharak Soltanian, Peter R. Kinget. 579-582 [doi]
• A phase noise minimization of CMOS VCOs over wide tuning range and large PVT variationsDaisuke Miyashita, Hiroki Ishikuro, Shouhei Kousai, Hiroyuki Kobayashi, Hideaki Majima, Kenichi Agawa, Mototsugu Hamada. 583-586 [doi]
• Process variability characterization and interconnect modelingHong-Ha Vuong, Yuhua Cheng. 586-587 [doi]
• Voltage-controlled oscillator in the coilFrank Zhang, Chen-Feng Chu, Peter R. Kinget. 587-590 [doi]
• Challenge: variability characterization and modeling for 65- to 90-nm processesHiroo Masuda, Shin-ichi Ohkawa, Atsushi Kurokawa, Masakazu Aoki. 593-599 [doi]
• A yield and speed enhancement scheme under within-die variations on 90nm LUT arrayKazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera. 601-604 [doi]
• Characterization of deep-submicron varactor mismatches in a digitally controlled oscillatorKhurram Waheed, Robert B. Staszewski. 605-608 [doi]
• Modeling leakage in ASIC librariesSusan Lichtensteiger, Larry Wissel, Jim Engel, Paul Sulva. 609-612 [doi]
• Design guideline for resistive termination of on-chip high-speed interconnectsAkira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera. 613-616 [doi]
• Will continued process-node shrinks kill high-performance analog design?Jafar Savoj, David Rich, Brett Forejt, Peter R. Kinget, Un-Ku Moon, Modest M. Oprysko, Behzad Razavi, Hisashi (Sam) Shichijo, Albert Wang. 616-617 [doi]
• A novel global interconnect method using nonlinear transmission linesJinsook Kim, Weiping Ni, Edwin C. Kan. 617-620 [doi]
• Foundries, EDA vendors, and designers: who shoulders the blame when a design doesn't work in the nano-scale and wireless era?Jamil Kawa, Yuhua Cheng, Hiroshi Iwai, Richard Goering, Michael Campbell, Raul Camposano, Jon Fields, Patrick Lin, Steve Lloyd, Joseph Sawicki, Ed Wan. 618-619 [doi]
• Analog behavioral modeling: fantasy, fad, or foundation for the future?Henry Chang, Colin McAndrew, Asad A. Abidi, Gayathri Bhagavatheeswaran, Jim Holmes, Kenneth S. Kundert, Alan H. Mantooth, Tony Strachan. 620-621 [doi]
• Filters and amplifiersDon Thelen, L. Richard Carley. 622-623 [doi]
• A second-order anti-aliasing prefilter for an SDR receiverAhmad Mirzaei, Rahim Bagheri, Saeed Chehrazi, Asad A. Abidi. 629-632 [doi]
• A 200 MS/s passive switched-capacitor FIR equalizer using a time-interleaved topologyNathaniel J. Guilar, Pak-Kim Lau, Paul J. Hurst, Stephen H. Lewis. 633-636 [doi]
• A wide-band active-RC filter with a fast tuning scheme for wireless communication receiversJinup Lim, Youngjoo Cho, Kyungsoo Jung, Jongmin Park, Joongho Choi, Jaewhui Kim. 637-640 [doi]
• Mixed-signal, 275 /spl deg/C instrumentation amplifier in bulk CMOSXinyu Yu, Steven L. Garverick. 641-644 [doi]
• A 15 GHz, 1.8V, variable-gain, modified Cherry-Hooper amplifierJustin P. Abbott, Calvin Plett, John W. M. Rogers. 645-648 [doi]
• A 1-V transient-free and DC-offset-canceled PGA with a 17.1-MHz constant bandwidth over 52-dB control range in 0.35-/spl mu/m CMOSPui-In Mak, Seng-Pan U, Rui Paulo Martins. 649-652 [doi]
• CMOS scaling and three-dimensional silicon integrationPhilippe Jansen, Larry Starr. 652-653 [doi]
• A low input impedance fully differential CMOS transresistance amplifier using cascode regulationArun Ravindran, Srikanth S. Mohan. 653-656 [doi]
• Three dimensional silicon integration using fine pitch interconnection, silicon processing and silicon carrier packaging technologyJohn U. Knickerbocker, Chirag S. Patel, Paul S. Andry, Cornelia K. Tsang, L. Paivikki Buchwalter, Edmund J. Sprogis, Hua Gan, Raymond R. Horton, Robert J. Polastre, Steven L. Wright, Christian D. Schuster, Christian W. Baks, Fuad E. Doany, Joanna Rosner, Steven Cordes. 659-662 [doi]
• Three-dimensional impedance engineering for mixed-signal system-on-chip applicationsKyuchul Chong, Xi Zhang, King-Ning Tu, Daquan Huang, Mau-Chung Frank Chang, Ya-Hong Xie. 663-666 [doi]
• Strain for CMOS performance improvementV. Chan, Ken Rim, Meikei Ieong, Sam Yang, Rajeev Malik, Young Way Teh, Min Yang, Qiqing Ouyang. 667-674 [doi]
• Device trends and implications on circuit design in advanced CMOS technologiesC. H. Diaz, K. H. Fung, Ying-Keung Leung, Chung-Cheng Wu, Chih-Ping Chao, G. J. Chern, Wesley L. Lin, C. Lee, Fang-shi Lai, Mi-Chang Chang, Yuan-Chen Sun. 675-679 [doi]
• Signal and data processorsDawn Fitzgerald, Bryan D. Ackland. 676-677 [doi]
• Digital signal processing in read channelsErich F. Haratsch, Z. A. Keirn. 683-690 [doi]
• An ASIC implementation of JPEG2000 codecLeibo Liu, Hongying Meng, Li Zhang, Zhihua Wang. 691-694 [doi]
• A continuous-time programmable digital FIR filterYee William Li, Kenneth L. Shepard, Yannis P. Tsividis. 695-698 [doi]
• An (8158, 7136) low-density parity-check encoderLowell H. Miles, Jody W. Gambles, Gary K. Maki, William E. Ryan, Sterling R. Whitaker. 699-702 [doi]
• Behavioral modeling and simulationJeanne Trinko Mechler, Larry Nagel. 702-703 [doi]
• Loosely coupled memory-based decoding architecture for low density parity check codesSe-Hyeon Kang, In-Cheol Park. 703-706 [doi]
• Modeling, simulation, and design of a multi-mode 2-10 Gb/sec fully adaptive serial link systemCarl W. Werner, C. Hoyer, Andrew Ho, Metha Jeeradit, Fred Chen, Bruno W. Garlepp, Bill Stonecypher, Simon Li, Akash Bansal, Amita Agarwal, Elad Alon, Vladimir Stojanovic, Jared Zerbe. 709-716 [doi]
• A behavioral level approach for nonlinear dynamic modeling of voltage-controlled oscillatorsRohan Batra, Peng Li, Lawrence T. Pileggi, Wanju Chiang. 717-720 [doi]
• Model topology formulation for nonlinear dynamic behavioral modelingYongfeng Feng, Wei Zheng 0002, Xiaoling Huang, H. Alan Mantooth. 721-724 [doi]
• A signal integrity-based link performance simulation platformYuming Tao, William Bereza, Rakesh H. Patel, Sergey Shumarayev, Tad A. Kwasniewski. 725-728 [doi]
• Analog techniquesDave Rich, Takahiro Miki. 728-729 [doi]
• Understanding injection locking in negative-resistance LC oscillators intuitively using nonlinear feedback analysisYayun Wan, Xiaolue Lai, Jaijeet S. Roychowdhury. 729-732 [doi]
• Design of a CMOS floating-gate resistor for highly linear amplifier and multiplier applicationsErhan Ozalevli, Paul E. Hasler. 735-73 [doi]
• A precision CMOS amplifier using floating-gates for offset cancellationSrinivasan Venkatesh 0003, Guillermo J. Serrano, Jordan D. Gray, Paul E. Hasler. 739-742 [doi]
• A bootstrapped switch for precise sampling of inputs with signal range beyond supply voltageDevrim Yilmaz Aksin, Mohammad A. Al-Shyoukh, Franco Maloberti. 743-746 [doi]
• A 1.2-V, 12-bit, 200M sample/s current-steering D/A converter in 90-nm CMOSTakeshi Ueno, Takafumi Yamaji, Tetsuro Itakura. 747-750 [doi]
• An ultra-low-power, temperature compensated voltage reference generatorGiuseppe de Vita, Giusseppe Iannaccone. 751-754 [doi]
• A switched capacitor regulated charge pump power supplyB. Robert Gregoire. 755-758 [doi]
• Nanometer design intricaciesRakesh H. Patel, Paul Billig. 758-759 [doi]
• A low noise, high power supply rejection low dropout regulator for wireless system-on-chip applicationsSiew Kuok Hoon, Shao-I Chen, Franco Maloberti, Jun Chen, Bhaskar Aravind. 759-762 [doi]
• Cellular handset integration - SIP vs. SOC and best design practices for SIPKevin Lyne. 765-770 [doi]
• A 90nm power optimization methodology and its' application to the ARM 1136SF-S microprocessorAurangzeb Khan, Philip Watson, George Kuo, D. Le, Trung-Kien Nguyen, Steven Yang, P. Bennet, Pokai Huang, Jaspal Gill, Demin Wang, Irfan Ahmed, Peter Tran, Helder Mak, Oanh Kim, Frank Martin, Yimu Fan, D. Ge, Joseph Kung, Vincent Shek. 771-774 [doi]
• Gated Decap: gate leakage control of on-chip decoupling capacitors in scaled technologiesYiran Chen, Hai Li, Kairshik Roy, Cheng-Kok Koh. 775-778 [doi]
• A comparison of electrical and optical clock networks in nanometer technologiesBryan D. Ackland, Behzad Razavi, Larry West. 779-782 [doi]
• Multi-protocol embedded PCS IP in a FPGA-SOCRamanand Venkata, Vinson Chan, Binh Ton, Chong Lee, Huy Ngo, Malik Kabani, Tam Nguyen, Arch Zaliznyak, Ning Xue, Steven Shen, Michael Zheng, Michael Lai, Steve Park, Lana Chan, Divya Vijayaraghavan, John Lam, Rakesh H. Patel. 783-786 [doi]
• Future wireless systemsEarl McCune, Edoardo Charbon. 786-787 [doi]
• Elastic shared resource scheduling SOC interconnect architecture for real-time systemMakoto Saen, Hiroshi Ueda, Masaru Hase, Eiji Yamamoto, Yoshihiro Mori, Hiroshi Hatae, Yuki Kondo, Seiji Miura, Itaru Nonomura, Naohiko Irie, Hiromi Watanabe. 787-790 [doi]
• Future wireless systems: UWB, 60GHz, and cognitive radiosDanijela Cabric, Mike Shuo-Wei Chen, David A. Sobel, Jing Yang 0004, Robert W. Brodersen. 793-796 [doi]
• An ultra-low power injection locked transmitter for wireless sensor networksYuen-Hui Chee, Ali M. Niknejad, Jan M. Rabaey. 797-800 [doi]
• A 6.5 GHz wideband CMOS low noise amplifier for multi-band useSaeed Chehrazi, Ahmad Mirzaei, Rahim Bagheri, Asad A. Abidi. 801-804 [doi]
• A 4-bit ultra-wideband beamformer with 4ps true time delay resolutionJonathan Roderick, Harish Krishnaswamy, Kenneth Newton, Hossein Hashemi. 805-808 [doi]
• A discrete time quad-band GSM/GPRS receiver in a 90nm digital CMOS processKhurram Muhammad, Y. C. Ho, Terry Mayhugh Jr., Chih-Ming Hung, Tom Jung, Imtinan Elahi, C. Lin, Irene Yuanying Deng, Chan Fernando, John L. Wallberg, Sudheer Vemulapalli, S. Larson, Thomas Murphy, Dirk Leipold, Patrick Cruise, J. Jaehnig, Meng-Chang Lee, Robert B. Staszewski, Roman Staszewski, Kenneth Maggio. 809-812 [doi]
• Advanced MOS modeling techniquesLaurence Nagel, Colin C. McAndrew. 812-813 [doi]
• A 5 GHz class-AB power amplifier in 90 nm CMOS with digitally-assisted AM-PM correctionYorgos Palaskas, Stewart S. Taylor, Stefano Pellerano, Ian A. Rippke, Ralph E. Bishop, Ashoke Ravi, Hasnain Lakdawala, Krishnamurthy Soumyanath. 813-816 [doi]
• SP-SOI: a third generation surface potential based compact SOI MOSFET ModelWeimin Wu, Xin Li, Hailing Wang, Gennady Gildenblat, Glen O. Workman, Surya Veeraraghavan, Colin C. McAndrew. 819-822 [doi]
• Unified non-quasi-static MOSFET model for large-signal and small-signal simulationsHailing Wang, Xin Li, Weimin Wu, Gennady Gildenblat, Ronald van Langevelde, G. D. J. Smitt, Andries J. Scholten, Dick B. M. Klaassen. 823-826 [doi]
• MOSFET harmonic distortion analysis up to the non-quasi-static frequency regimeYouichi Takeda, Dondee Navarro, Shingo Chiba, Michiko Miura-Mattausch, Hans Jürgen Mattausch, Tatsuya Ohguro, Takahiro Iizuka, Masahiko Taguchi, Shigetaka Kumashiro, Shunsuke Miyamoto. 827-830 [doi]
• Modeling well edge proximity effect on highly-scaled MOSFETsYi-Ming Sheu, Ke-Wei Su, Sheng-Jier Yang, Hsien-Te Chen, Chih-Chiang Wang, Ming-Jer Chen, S. Liu. 831-834 [doi]
• Modeling and optimization approach to robust and low-power FinFET SRAM design in nanoscale eraAditya Bansal, Saibal Mukhopadhyay, Kairshik Roy. 835-838 [doi]