Jared Zerbe - researchr alias

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Viewing Publication 1 - 19 from 19

2015

A 40 Gb/s Serial Link Transceiver in 28 nm CMOS TechnologyReza Navid, E.-Hung Chen, Masum Hossain, Brian S. Leibowitz, Jihong Ren, Chuen-huei Adam Chou, Barry Daly, Marko Aleksic, Bruce Su, Simon Li, Makarand Shirasgaonkar, Fred Heaton, Jared Zerbe, John C. Eble. jssc, 50(4):814-827, 2015. [doi]

2014

A 40-Gb/s serial link transceiver in 28-nm CMOS technologyE.-Hung Chen, Masum Hossain, Brian S. Leibowitz, Reza Navid, Jihong Ren, Chuen-huei Adam Chou, Barry Daly, Marko Aleksic, Bruce Su, Simon Li, Makarand Shirasgaonkar, Fred Heaton, Jared Zerbe, John C. Eble. vlsic 2014: 1-2 [doi]

A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filteringMasum Hossain, E.-Hung Chen, Reza Navid, Brian S. Leibowitz, Chuen-huei Adam Chou, Simon Li, Myeong-Jae Park, Jihong Ren, Barry Daly, Bruce Su, Makarand Shirasgaonkar, Fred Heaton, Jared Zerbe, John C. Eble. vlsic 2014: 1-2 [doi]

A Fast-Lock, Jitter Filtering All-Digital DLL Based Burst-Mode Memory InterfaceMasum Hossain, Farrukh Aquil, Pak Shing Chau, Brian Tsang, Phuong Le, Jason Wei, Teva Stone, Barry Daly, Chanh Tran, John C. Eble, Kurt Knorpp, Jared Zerbe. jssc, 49(4):1048-1062, 2014. [doi]

2012

2011

2010

Equalizer design and performance trade-offs in ADC-based serial linksJaeha Kim, Jihong Ren, Brian S. Leibowitz, Patrick Satarzadeh, Ali-Azam Abbasfar, Jared Zerbe. cicc 2010: 1-8 [doi]

2009

2008

Near-Optimal Equalizer and Timing Adaptation for I/O Links Using a BER-Based MetricE.-Hung Chen, Jihong Ren, Brian S. Leibowitz, Haechang Lee, Qi Lin, Kyung Suk Oh, Frank Lambrecht, Vladimir Stojanovic, Jared Zerbe, Chih-Kong Ken Yang. jssc, 43(9):2144-2156, 2008. [doi]

2007

2006

Improving CDR Performance via EstimationHaechang Lee, Akash Bansal, Yohan Frans, Jared Zerbe, S. Sidiropoulos, M. Horowitz. isscc 2006: 1296-1303 [doi]

2005

Modeling, simulation, and design of a multi-mode 2-10 Gb/sec fully adaptive serial link systemCarl W. Werner, C. Hoyer, Andrew Ho, Metha Jeeradit, Fred Chen, Bruno W. Garlepp, Bill Stonecypher, Simon Li, Akash Bansal, Amita Agarwal, Elad Alon, Vladimir Stojanovic, Jared Zerbe. cicc 2005: 709-716 [doi]

2003

Transition-limiting codes for 4-PAM signaling in high speed serial linksAnthony G. Bessios, William F. Stonecypher, Amita Agarwal, Jared Zerbe. globecom 2003: 3747-3751 [doi]

1998

A process-independent, 800-MB/s, DRAM byte-wide interface featuring command interleaving and concurrent memory operationMatthew M. Griffin, Jared Zerbe, Grace Tsang, Michael Ching, Clemenz L. Portmann. jssc, 33(11):1741-1751, 1998. [doi]

1994

A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAMThomas H. Lee, Kevin S. Donnelly, John T. C. Ho, Jared Zerbe, Mark Johnson, Tom Ishikawa. jssc, 29(12):1491-1496, December 1994. [doi]

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