Table of Contents

• On-chip measurement of data jitter with sub-picosecond accuracy for 10Gb/s multilane CDRsJoshua Liang, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura. 1-2 [doi]
• A 960MS/s DAC with 80dB SFDR in 20nm CMOS for multi-mode baseband wireless transmitterWei-Hsin Tseng, Pao-Cheng Chiu. 1-2 [doi]
• A 0.8V, 560fJ/bit, 14Gb/s injection-locked receiver with input duty-cycle distortion tolerable edge-rotating 5/4X sub-rate CDR in 65nm CMOSHao Li, Shuai Chen, Liqiong Yang, Rui Bai, Weiwu Hu, Freeman Y. Zhong, Samuel Palermo, Patrick Yin Chiang. 1-2 [doi]
• A 4K×2K@60fps multi-standard TV SoC processor with integrated HDMI/MHL receiverChi-Cheng Ju, Tsu-Ming Liu, Huaide Wang, Yung-Chang Chang, Chih-Ming Wang, Chang-Lin Hsieh, Brian Liu, Hue-Min Lin, Chia-Yun Cheng, Chun-Chia Chen, Min-Hao Chiu, Sheng-Jen Wang, Ping Chao, Meng-Jye Hu, Ryan Yeh, Ted Chuang, Hsiu-Yi Lin, Chung-Hung Tsai. 1-2 [doi]
• 2 fully-integrated neuromodulation SoC combining 64 acquisition channels with digital compression and simultaneous dual stimulationDaniel J. Yeager, William Biederman, Nathan Narevsky, Jaclyn Leverett, Ryan Neely, Jose M. Carmena, Elad Alon, Jan M. Rabaey. 1-2 [doi]
• A Vocabulary Forest-based object matching processor with 2.07M-vec/s throughput and 13.3nJ/vector energy in full-HD resolutionKyuho Jason Lee, Gyeonghoon Kim, Junyoung Park, Hoi-Jun Yoo. 1-2 [doi]
• A 48 fJ/CS, 74 dB SNDR, 87 dB SFDR, 85 dB THD, 30 MS/s pipelined ADC using hybrid dynamic amplifierHariprasath Venkatram, Taehwan Oh, Kazuki Sobue, Koichi Hamashita, Un-Ku Moon. 1-2 [doi]
• Early detection and repair of VRT and aging DRAM bits by margined in-field BISTBendik Kleveland, Jeong Choi, Jeff Kumala, Pascal Adam, Patrick Chen, Rajesh Chopra, Antonio Cruz, Ronald B. David, Ashish Dixit, Sinan Doluca, Mark Hendrickson, Ben Lee, Ming Liu, Michael John Miller, Mike Morrison, Byeong Cheol Na, Jay Patel, Dipak K. Sikdar, Michael Sporer, Clement Szeto, Anju Tsao, Jianguang Wang, Daniel Yau, Wesley Yu. 1-2 [doi]
• Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPUHiroki Noguchi, Kazutaka Ikegami, Naoharu Shimomura, Tetsufumi Tanamoto, Junichi Ito, Shinobu Fujita. 1-2 [doi]
• Design technologies for a 1.2V 2.4Gb/s/pin high capacity DDR4 SDRAM with TSVsReum Oh, ByungHyun Lee, Sang-Woong Shin, Wonil Bae, Hundai Choi, Indal Song, Yun Sang Lee, Jung Hwan Choi, Chi-Wook Kim, Seong-Jin Jang, Joo-Sun Choi. 1-2 [doi]
• An ASIC for readout of post-processed thin-film MEMS resonators by employing capacitive interfacing and active parasitic cancellationLiechao Huang, Warren Rieutort-Louis, Alexandra Gualdino, Laura Teagno, Yingzhe Hu, Jaoa Mouro, Josue Sanz-Robinson, James C. Sturm, Sigurd Wagner, Virginia Chu, Joao Pedro Conde, Naveen Verma. 1-2 [doi]
• A monolithically-integrated optical transmitter and receiver in a zero-change 45nm SOI processMichael Georgas, Benjamin Moss, Chen Sun, Jeffrey Shainline, Jason Orcutt, Mark Wade, Yu-Hsin Chen, Kareem Nammari, Jonathan Leu, A. Srinivasan, Rajeev J. Ram, Milos Popovic, Vladimir Stojanovic. 1-2 [doi]
• A 6.5/11/17.5/30-GHz high throughput interferometer-based reactance sensors using injection-locked oscillators and ping-pong nested choppingJun-Chau Chien, Mekhail Anwar, Erh-Chia Yeh, Luke P. Lee, Ali M. Niknejad. 1-2 [doi]
• Application-aware solid-state drives (SSDs) with adaptive codingShuhei Tanakamaru, Yuta Kitamura, Senju Yamazaki, Tsukasa Tokutomi, Ken Takeuchi. 1-2 [doi]
• A 2.7GHz to 7GHz fractional-N LCPLL utilizing multimetal layer SoC technology in 28nm CMOSChang-Hyeon Lee, Lindel Kabalican, Yan Ge, Hendra Kwantono, Greg Unruh, Mark Chambers, Ichiro Fujimori. 1-2 [doi]
• 2 polynomials in 22nm tri-gate CMOSSanu Mathew, Sudhir Satpathy, Vikram Suresh, Himanshu Kaul, Mark Anders, Gregory K. Chen, Amit Agarwal, Steven Hsu, Ram Krishnamurthy. 1-2 [doi]
• R-processor: 0.4V resilient processor with a voltage-scalable and low-overhead in-situ error detection and correction technique in 65nm CMOSSeongjong Kim, Mingoo Seok. 1-2 [doi]
• A receiver architecture for intra-band carrier aggregationSy-Chyuan Hwu, Behzad Razavi. 1-2 [doi]
• A 400MHz 10Mbps D-BPSK receiver with a reference-less dynamic phase-to-amplitude demodulation techniqueYi-Lin Tsai, Jian-You Chen, Bang-Cyuan Wang, Tzu-Yu Yeh, Tsung-Hsien Lin. 1-2 [doi]
• An 11.5-ENOB 100-MS/s 8mW dual-reference SAR ADC in 28nm CMOSMichael Inerfield, Abhishek Kamath, Feng Su, Jason Hu, Xinyu Yu, Victor Fong, Omar Alnaggar, Fang Lin, Tom Kwan. 1-2 [doi]
• A direct AC-DC and DC-DC cross-source energy harvesting circuit with analog iterating-based MPPT technique with 72.5% conversion efficiency and 94.6% tracking efficiencyTzu-Chi Huang, Ming-Jhe Du, Kuei-Liang Lin, Shao Siang Ng, Ke-Horng Chen, Chin-Long Wey, Ying-Hsin Lin, Tsung-Yen Tsai, Chen-Chih Huang, Chao-Cheng Lee, Jui-Lung Chen, Hung-Wei Chen. 1-2 [doi]
• A power-harvesting pad-less mm-sized 24/60GHz passive radio with on-chip antennasMaryam Tabesh, Mustafa Rangwala, Ali M. Niknejad, Amin Arbabian. 1-2 [doi]
• A peripheral switchable 3D stacked CMOS image sensorCharles Chih-Min Liu, Chin-Hao Chang, Honyih Tu, Calvin Yi-Ping Chao, Fu-Lung Hsueh, Szu-Ying Chen, Vincent Hsu, Jen-Cheng Liu, Dun-Nien Yaung, Shou-Gwo Wuu. 1-2 [doi]
• An exact measurement and repair circuit of TSV connections for 128GB/s high-bandwidth memory(HBM) stacked DRAMDong Uk Lee, Kyung-whan Kim, Kwan-Weon Kim, Kang Seol Lee, Sang Jin Byeon, Jin-Hee Cho, Han Ho Jin, Sang Kyun Nam, Jaejin Lee, Jun Hyun Chun, Sungjoo Hong. 1-2 [doi]
• A 12b 160MS/s synchronous two-step SAR ADC achieving 20.7fJ/step FoM with opportunistic digital background calibrationYuan Zhou, Benwei Xu, Yun Chiu. 1-2 [doi]
• A 40-Gb/s serial link transceiver in 28-nm CMOS technologyE.-Hung Chen, Masum Hossain, Brian S. Leibowitz, Reza Navid, Jihong Ren, Chuen-huei Adam Chou, Barry Daly, Marko Aleksic, Bruce Su, Simon Li, Makarand Shirasgaonkar, Fred Heaton, Jared Zerbe, John C. Eble. 1-2 [doi]
• A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distributionTakushi Hashida, Yasumoto Tomita, Yuuki Ogata, Kosuke Suzuki, Shigeto Suzuki, Takanori Nakao, Yuji Terao, Satofumi Honda, Sota Sakabayashi, Ryuichi Nishiyama, Akihiko Konmoto, Yoshitomo Ozeki, Hiroyuki Adachi, Hisakatsu Yamaguchi, Yoichi Koyanagi, Hirotaka Tamura. 1-2 [doi]
• A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOSTakayuki Shibasaki, Win Chaivipas, Yanfei Chen, Yoshiyasu Doi, Takayuki Hamada, Hideki Takauchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura. 1-2 [doi]
• nd generation embedded DRAM with 4X lower self refresh power in 22nm Tri-Gate CMOS technologyMesut Meterelliyoz, Fuad H. Al-amoody, Umut Arslan, Fatih Hamzaoglu, Luke Hood, Manoj B. Lal, Jeffrey L. Miller, Anand Ramasundar, Dan Soltman, Ifar Wan, Yih Wang, Kevin Zhang. 1-2 [doi]
• A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filteringMasum Hossain, E.-Hung Chen, Reza Navid, Brian S. Leibowitz, Chuen-huei Adam Chou, Simon Li, Myeong-Jae Park, Jihong Ren, Barry Daly, Bruce Su, Makarand Shirasgaonkar, Fred Heaton, Jared Zerbe, John C. Eble. 1-2 [doi]
• A Column-Row-Parallel ASIC architecture for 3D wearable / portable medical ultrasonic imagingKailiang Chen, Hae-Seung Lee, Charles G. Sodini. 1-2 [doi]
• A 97.3 dB SNR, 600 kHz BW, 31mW multibit continuous time ΔΣ ADCAbhishek Bandyopadhyay, Robert Adams, Khiem Nguyen, Paul Baginski, David Lamb, Thomas Tansley. 1-2 [doi]
• A 65-nm 0.5-V 17-pJ/frame.pixel DPS CMOS image sensor for ultra-low-power SoCs achieving 40-dB dynamic rangeDavid Bol, Guerric de Streel, François Botman, Angelo Kuti Lusala, Numa Couniot. 1-2 [doi]
• A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converterMrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena, Brian Young, Woo-seok Choi, Pavan Kumar Hanumolu. 1-2 [doi]
• A monolithically-integrated chip-to-chip optical link in bulk CMOSChen Sun, Michael Georgas, Jason Orcutt, Benjamin Moss, Yu-Hsin Chen, Jeffrey Shainline, Mark Wade, Karan Mehta, Kareem Nammari, Erman Timurdogan, Daniel Miller, Ofer Tehar-Zahav, Zvi Sternberg, Jonathan Leu, Johanna Chong, Reha Bafrali, Gurtej Sandhu, Michael Watts, Roy Meade, Milos Popovic, Rajeev J. Ram, Vladimir Stojanovic. 1-2 [doi]
• A 10-25MHz, 600mA buck converter using time-based PID compensator with 2µA/MHz quiescent current, 94% peak efficiency, and 1MHz BWQadeer Ahmad Khan, Seong Joong Kim, Mrunmay Talegaonkar, Amr Elshazly, Arun Rao, Nathanael Griesert, Greg Winter, William McIntyre, Pavan Kumar Hanumolu. 1-2 [doi]
• A 40-MHz 85.8%-peak-efficiency switching-converter-only dual-phase envelope modulator for 2-W 10-MHz LTE power amplifierJoseph Sankman, Minkyu Song, Dongsheng Ma. 1-2 [doi]
• An 8.5MHz 67.2dB SNDR CTDSM with ELD compensation embedded twin-T SAB and circular TDC-based quantizer in 90nm CMOSChan-Hsiang Weng, Tzu-An Wei, Erkan Alpman, Chang-Tsung Fu, Yi-Ting Tseng, Tsung-Hsien Lin. 1-2 [doi]
• A +22dBm IIP3 and 3.5dB NF wideband receiver with RF and baseband blocker filtering techniquesHajir Hedayati, Vladimir Aparin, Kamran Entesari. 1-2 [doi]
• A 266nW multi-chopper amplifier with 1.38 noise efficiency factor for neural signal recordingYen-Po Chen, David Blaauw, Dennis Sylvester. 1-2 [doi]
• A 4.68Gb/s belief propagation polar decoder with bit-splitting register fileYoun Sung Park, Yaoyu Tao, Shuanghong Sun, Zhengya Zhang. 1-2 [doi]
• A PVT-variation tolerant fully integrated 60 GHz transceiver for IEEE 802.11adTakayuki Tsukizawa, Atsushi Yoshimoto, Hiroshi Komori, Kenji Miyanaga, Ryo Kitamura, Yohei Morishita, Masatake Irie, Yoichi Nagaso, Takeaki Watanabe, Koji Takinami, Noriaki Saito. 1-2 [doi]
• A 0.7V resistive sensor with temperature/voltage detection function in 16nm FinFET technologiesJaw-Juinn Horng, Szu-Lin Liu, Amit Kundu, Chin-Ho Chang, Chung-Hui Chen, Herman Chiang, Yung-Chow Peng. 1-2 [doi]
• An 18 b 5 MS/s SAR ADC with 100.2 dB dynamic rangeAlan Bannon, Christopher Peter Hurrell, Derek Hummerston, Colin Lyden. 1-2 [doi]
• 7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring TechniqueKentaro Yoshioka, Ryo Saito, Takumi Danjo, Sanroku Tsukamoto, Hiroki Ishikuro. 1-2 [doi]
• A 915MHz, 6Mb/s, 80pJ/b BFSK receiver with -76dBm sensitivity for high data rate wireless sensor networksRonghua Ni, Kartikeya Mayaram, Terri S. Fiez. 1-2 [doi]
• A 0.37-to-46.5GHz frequency synthesizer for software-defined radios in 65nm CMOSJun Yin, Howard C. Luong. 1-2 [doi]
• 15.4b incremental sigma-delta capacitance-to-digital converter with zoom-in 9b asynchronous SARSechang Oh, Wanyeong Jung, Kaiyuan Yang, David Blaauw, Dennis Sylvester. 1-2 [doi]
• A 500MHz blind classification processor for cognitive radios in 40nm CMOSFang-Li Yuan, Tsung-Han Yu, Dejan Markovic. 1-2 [doi]
• A 12mW all-digital PLL based on class-F DCO for 4G phones in 28nm CMOSFeng-Wei Kuo, Ron Chen, Kyle Yen, Hsien-Yuan Liao, Chewnpu Jou, Fu-Lung Hsueh, Masoud Babaie, Robert Bogdan Staszewski. 1-2 [doi]
• A fully-differential capacitive touch controller with input common-mode feedback for symmetric display noise cancellationKi-Duk Kim, Sanghyub Kang, Yoon Kyung Choi, Kyung-Hoon Lee, Choong-Hoon Lee, Jin-chul Lee, Michael Choi, Kyungjun Ko, Joonwoo Jung, Namgu Park, Ho-Jin Park, Gyoocheol Hwang. 1-2 [doi]
• A millimeter-scale wireless imaging system with continuous motion detection and energy harvestingGyouho Kim, Yoonmyung Lee, Zhiyoong Foo, Pat Pannuto, Ye-Sheng Kuo, Benjamin P. Kempke, Mohammad Hassan Ghaed, Suyoung Bang, Inhee Lee, Yejoong Kim, Seokhyeon Jeong, Prabal Dutta, Dennis Sylvester, David Blaauw. 1-2 [doi]
• A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with -106dBc/Hz In-band noise using time amplifier based TDCAhmed Elkholy, Tejasvi Anand, Woo-seok Choi, Amr Elshazly, Pavan Kumar Hanumolu. 1-2 [doi]
• A 13.1GOPS/mW 16-core processor for software-defined radios in 40nm CMOSFang-Li Yuan, Dejan Markovic. 1-2 [doi]
• Energy-recycling integrated 6.78-Mbps data 6.3-mW power telemetry over a single 13.56-MHz inductive linkSohmyung Ha, Chul Kim, Jongkil Park, Siddharth Joshi, Gert Cauwenberghs. 1-2 [doi]
• A local EM-analysis attack resistant cryptographic engine with fully-digital oscillator-based tamper-access sensorNoriyuki Miura, Daisuke Fujimoto, Daichi Tanaka, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki, Makoto Nagata. 1-2 [doi]
• Technology development for printed LSIs based on organic semiconductorsJ. Takeya, M. Uno. 1-4 [doi]
• A quad-channel 112-128 Gb/s coherent transmitter in 40 nm CMOSAdesh Garg, Ullas Singh, Nick Huang, Wayne Wong, Bin Liu, Zhi Chao Huang, Afshin Momtaz, Jun Cao. 1-2 [doi]
• A 2.9mW, +/- 85ppm accuracy reference clock generator based on RC oscillator with on-chip temperature calibrationYuji Satoh, Hiroyuki Kobayashi, Takeshi Miyaba, Shouhei Kousai. 1-2 [doi]
• A 94GHz duobinary keying wireless transceiver in 65nm CMOSYu-Lun Chen, Chiro Kao, Pen-Jui Peng, Jri Lee. 1-2 [doi]
• A single-chip encrypted wireless 12-lead ECG smart shirt for continuous health monitoringTim Morrison, Jason Silver, Brian Otis. 1-2 [doi]
• A 6.67mW sparse coding ASIC enabling on-chip learning and inferenceJung Kuk Kim, Phil Knag, Thomas Chen, Zhengya Zhang. 1-2 [doi]
• A self-aware processor SoC using energy monitors integrated into power converters for self-adaptationYildiz Sinangil, Sabrina M. Neuman, Mahmut E. Sinangil, Nathan Ickes, George Bezerra, Eric Lau, Jason E. Miller, Henry Hoffmann, Srinivas Devadas, Anantha P. Chandraksan. 1-2 [doi]
• A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvementRomesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Ahmed Elkholy, Woo-seok Choi, Amr Elshazly, Pavan Kumar Hanumolu. 1-2 [doi]
• 320×240 oversampled digital single photon counting image sensorNeale A. W. Dutton, Luca Parmesan, Andrew J. Holmes, Lindsay A. Grant, Robert K. Henderson. 1-2 [doi]
• A 70 dB SNDR 200 MS/s 2.3 mW dynamic pipelined SAR ADC in 28nm digital CMOSBob Verbruggen, Kazuaki Deguchi, Badr Malki, Jan Craninckx. 1-2 [doi]
• A low power and ultra high reliability LDPC error correction engine with Digital Signal Processing for embedded NAND Flash Controller in 40nm COMSWei Lin, Shao-Wei Yen, Yu-Cheng Hsu, Yu-Hsiang Lin, Li-Chun Liang, Tien-Ching Wang, Pei-Yu Shih, Kuo-Hsin Lai, Kuo-Yi Cheng, Chun-Yen Chang. 1-2 [doi]
• A 64×64 1200fps CMOS ion-image sensor with suppressed fixed-pattern-noise for accurate high-throughput DNA sequencingXiwei Huang, Fei Wang, Jing Guo, Mei Yan, Hao Yu, Kiat Seng Yeo. 1-2 [doi]
• 2, 11GS/s 9-bit interleaved DAC in 28nm FDSOI with >50dB SFDR across NyquistErik Olieman, Anne-Johan Annema, Bram Nauta. 1-2 [doi]
• ±3% voltage variation and 95% efficiency 28nm constant on-time controlled step-down switching regulator directly supplying to Wi-Fi systemsWei-Chung Chen, Yung-Sheng Huang, Meng-Wei Chien, Ying-Wei Chou, Hsin-Chieh Chen, Yi-Ping Su, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Tsung-Yen Tsai, Chen-Chih Huang, Chao-Cheng Lee. 1-2 [doi]
• 92% start-up time reduction by variation-tolerant chirp injection (CI) and negative resistance booster (NRB) in 39MHz crystal oscillatorShunta Iguchi, Hiroshi Fuketa, Takayasu Sakurai, Makoto Takamiya. 1-2 [doi]
• A 0.63ps, 12b, synchronous cyclic TDC using a time adder for on-chip jitter measurement of a SoC in 28nm CMOS technologySung Jin Kim, Taeik Kim, Hojin Park. 1-2 [doi]
• A 500 MHz, 68% efficient, fully on-die digitally controlled buck Voltage Regulator on 22nm Tri-Gate CMOSHarish Krishnamurthy, Vaibhav A. Vaidya, Pavan Kumar, George E. Matthew, Sheldon Weng, Bharani Thiruvengadam, Wayne Proefrock, Krishnan Ravichandran, Vivek De. 1-2 [doi]
• DataCenter 2020: Near-memory acceleration for data-oriented applicationsEdward Doller, Ameen Akel, Jeffrey Wang, Ken Curewitz, Sean Eilert. 1-4 [doi]
• A 2GHz-to-7.5GHz quadrature clock-generator using digital delay locked loops for multi-standard I/Os in 14nm CMOSAmr Elshazly, Ajay Balankutty, Yan-Yu Huang, Kai Yu, Frank O'Mahony. 1-2 [doi]
• ReRAM-based 4T2R nonvolatile TCAM with 7x NVM-stress reduction, and 4x improvement in speed-wordlength-capacity for normally-off instant-on filter-based search engines used in big-data processingLi-Yue Huang, Meng-Fan Chang, Ching-Hao Chuang, Chia-Chen Kuo, Chien-Fu Chen, Geng-Hau Yang, Hsiang-Jen Tsai, Tien-Fu Chen, Shyh-Shyuan Sheu, Keng-Li Su, Frederick T. Chen, Tzu-Kun Ku, Ming-Jinn Tsai, Ming-Jer Kao. 1-2 [doi]
• A 4.7T/11.1T NMR compliant wirelessly programmable implant for bio-artificial pancreas in vivo monitoringWalker J. Turner, Rizwan Bashirullah. 1-2 [doi]
• rd order CT-ΔΣ modulator using VCO-based integratorsBrian Young, Karthik Reddy, Sachin Rao, Amr Elshazly, Tejasvi Anand, Pavan Kumar Hanumolu. 1-2 [doi]
• A 32-bit CPU with zero standby power and 1.5-clock sleep/2.5-clock wake-up achieved by utilizing a 180-nm C-axis aligned crystalline In-Ga-Zn oxide transistorAtsuo Isobe, Hikaru Tamura, Kiyoshi Kato, Takuro Ohmaru, Wataru Uesugi, Takahiko Ishizu, Tatsuya Onuki, Kazuaki Ohshima, Takanori Matsuzaki, Atsushi Hirose, Yasutaka Suzuki, Naoaki Tsutsui, Tomoaki Atsumi, Yutaka Shionoiri, Gensuke Goto, Jun Koyama, Masahiro Fujita, Shunpei Yamazaki. 1-2 [doi]
• Foreword: Welcome to the 2014 Symposium on VLSI CircuitsVivek De, Hideyuki Kabuo. 1-2 [doi]
• A 3nV/vHz programmable gain/BW mixed-signal 4th order Chebyshev high-pass filter for ADSL/VDSL analog front end in 28nm CMOSHarsh Mehta, Gautham Krishnamurthy, Michael Inerfield, Fang Lin, Tom Kwan. 1-2 [doi]
• A 13.56MHz wireless power transfer system with reconfigurable resonant regulating rectifier and wireless power control for implantable medical devicesXing Li, Chi-Ying Tsui, Wing-Hung Ki. 1-2 [doi]
• A 3.7M-pixel 1300-fps CMOS image sensor with 5.0G-pixel/s high-speed readout circuitShunsuke Okura, Osamu Nishikido, Yusuke Sadanaga, Yasuhiro Kosaka, Norihiko Araki, Kazuhiro Ueda, Masanori Tachibana, Fukashi Morishita. 1-2 [doi]
• A 352Gb/s inductive-coupling DRAM/SoC interface using overlapping coils with phase division multiplexing and ultra-thin fan-out wafer level packageAbdul Raziz Junaidi, Yasuhiro Take, Tadahiro Kuroda. 1-2 [doi]
• 2MLP) for big data analysis and applicationsChang-Hung Tsai, Tung-Yu Wu, Shu-Yu Hsu, Chia-Ching Chu, Fang-Ju Ku, Ying-Siou Laio, Chih-Lung Chen, Wing Hung Wong, Hsie-Chia Chang, Chen-Yi Lee. 1-2 [doi]
• Low power battery supervisory circuit with adaptive battery health monitorInhee Lee, Yoonmyung Lee, Dennis Sylvester, David Blaauw. 1-2 [doi]
• An on-chip 72×60 angle-sensitive single photon image sensor array for lens-less time-resolved 3-D fluorescence lifetime imagingChanghyuk Lee, Ben Johnson, Alyosha C. Molnar. 1-2 [doi]
• An N-path filter enhanced low phase noise ring VCOChunyang Zhai, Jeffrey Fredenburg, John Bell, Michael P. Flynn. 1-2 [doi]
• A 12-bit 210-MS/s 5.3-mW pipelined-SAR ADC with a passive residue transfer techniqueChin-Yu Lin, Tai-Cheng Lee. 1-2 [doi]
• A 48-mW 18-Gb/s fully integrated CMOS optical receiver with photodetector and adaptive equalizerQuan Pan, Zhengxiong Hou, Yipeng Wang, Yan Lu, Wing-Hung Ki, Keh-Chung Wang, C. Patrick Yue. 1-2 [doi]
• An ultra-low-power 2-step wake-up receiver for IEEE 802.15.4g wireless sensor networksTakayuki Abe, Takashi Morie, Kazutoshi Satou, Daisuke Nomasaki, Shigeki Nakamura, Yoichiro Horiuchi, Koji Imamura. 1-2 [doi]
• An impedance and multi-wavelength near-infrared spectroscopy IC for non-invasive blood glucose estimationKiseok Song, Unsoo Ha, Seongwook Park, Hoi-Jun Yoo. 1-2 [doi]
• A 0.4V 2.02fJ/conversion-step 10-bit hybrid SAR ADC with time-domain quantizer in 90nm CMOSYan-Jiun Chen, Chih-Cheng Hsieh. 1-2 [doi]
• An implantable continuous glucose monitoring microsystem in 0.18µm CMOSMeisam Honarvar Nazari, Muhammad Mujeeb-U.-Rahman, Axel Scherer. 1-2 [doi]
• A 23mW, 73dB dynamic range, 80MHz BW continuous-time delta-sigma modulator in 20nm CMOSStacy Ho, Chi-Lun Lo, Zhiyu Ru, Jialin Zhao. 1-2 [doi]
• Low VMIN 20nm embedded SRAM with multi-voltage wordline control based read and write assist techniquesMudit Bhargava, Y. K. Chong, Vincent Schuppe, Bikas Maiti, Martin Kinkade, Hsin-Yu Chen, Andy W. Chen, Sanjay Mangal, Jacek Wiatrowski, Gerald Gouya, Abhishek Baradia, Sriram Thyagarajan, Gus Yeung. 1-2 [doi]
• A 1.2µW SIMO energy harvesting and power management unit with constant peak inductor current control achieving 83-92% efficiency across wide input and output voltagesAatmesh Shrivastava, Yogesh K. Ramadass, Sudhanshu Khanna, Steven Bartling, Benton H. Calhoun. 1-2 [doi]
• A 12-bit hybrid DAC with 8GS/s unrolled pipeline delta-sigma modulator achieving >75dB SFDR over 500MHz in 65nm CMOSShiyu Su, Tu-I. Tsai, Praveen Kumar Sharma, Mike Shuo-Wei Chen. 1-2 [doi]
• A 512-kb 1-GHz 28-nm partially write-assisted dual-port SRAM with self-adjustable negative bias bitlineShinji Tanaka, Yuichiro Ishii, Makoto Yabuuchi, Toshiaki Sano, Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Hirotoshi Sato. 1-2 [doi]