Brian Young - researchr alias

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Viewing Publication 1 - 28 from 28

2017

A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOSMrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena, Brian Young, Woo-seok Choi, Pavan Kumar Hanumolu. jssc, 52(9):2306-2320, 2017. [doi]

2015

A 54mW 1.2GS/s 71.5dB SNDR 50MHz BW VCO-based CT ΔΣ ADC using dual phase/frequency feedback in 65nm CMOSKarthikeyan Reddy, Siladitya Dey, Sachin Rao, Brian Young, Praveen Prabha, Pavan Kumar Hanumolu. vlsic 2015: 256 [doi]

2014

A 5 Gb/s, 10 ns Power-On-Time, 36 $\mu$W Off-State Power, Fast Power-On Transmitter for Energy Proportional LinksTejasvi Anand, Amr Elshazly, Mrunmay Talegaonkar, Brian Young, Pavan Kumar Hanumolu. jssc, 49(10):2243-2258, 2014. [doi]

A Noise-Shaping Time-to-Digital Converter Using Switched-Ring Oscillators - Analysis, Design, and Measurement TechniquesAmr Elshazly, Sachin Rao, Brian Young, Pavan Kumar Hanumolu. jssc, 49(5):1184-1197, 2014. [doi]

A Deterministic Digital Background Calibration Technique for VCO-Based ADCsSachin Rao, Karthikeyan Reddy, Brian Young, Pavan Kumar Hanumolu. jssc, 49(4):950-960, 2014. [doi]

A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked LoopGuanghua Shu, Saurabh Saxena, Woo-seok Choi, Mrunmay Talegaonkar, Rajesh Inti, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu. jssc, 49(4):1036-1047, 2014. [doi]

A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converterMrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena, Brian Young, Woo-seok Choi, Pavan Kumar Hanumolu. vlsic 2014: 1-2 [doi]

rd order CT-ΔΣ modulator using VCO-based integratorsBrian Young, Karthik Reddy, Sachin Rao, Amr Elshazly, Tejasvi Anand, Pavan Kumar Hanumolu. vlsic 2014: 1-2 [doi]

2013

2012

A 13b 315fsrms 2mW 500MS/s 1MHz bandwidth highly digital time-to-digital converter using switched ring oscillatorsAmr Elshazly, Sachin Rao, Brian Young, Pavan Kumar Hanumolu. isscc 2012: 464-466 [doi]

A 1.5GHz 890μW digital MDLL with 400fsrms integrated jitter, -55.6dBc reference spur and 20fs/mV supply-noise sensitivity using 1b TDCAmr Elshazly, Rajesh Inti, Brian Young, Pavan Kumar Hanumolu. isscc 2012: 242-244 [doi]

Quality Metric for Parasternal Long Axis B-Mode EchocardiogramsSri-Kaushik Pavani, Navneeth Subramanian, Mithun Das Gupta, Pavan Annangi, Satish C. Govind, Brian Young. miccai 2012: 478-485 [doi]

A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizerKarthikeyan Reddy, Sachin Rao, Rajesh Inti, Brian Young, Amr Elshazly, Mrunmay Talegaonkar, Pavan Kumar Hanumolu. isscc 2012: 152-154 [doi]

A 16-mW 78-dB SNDR 10-MHz BW CT Delta Sigma ADC Using Residue-Cancelling VCO-Based QuantizerKarthikeyan Reddy, Sachin Rao, Rajesh Inti, Brian Young, Amr Elshazly, Mrunmay Talegaonkar, Pavan Kumar Hanumolu. jssc, 47(12):2916-2927, 2012. [doi]

2011

A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibrationAmr Elshazly, Rajesh Inti, Wenjing Yin, Brian Young, Pavan Kumar Hanumolu. isscc 2011: 92-94 [doi]

A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background CalibrationAmr Elshazly, Rajesh Inti, Wenjing Yin, Brian Young, Pavan Kumar Hanumolu. jssc, 46(12):2759-2771, 2011. [doi]

A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOSRajesh Inti, Amr Elshazly, Brian Young, Wenjing Yin, Marcel A. Kossel, Thomas Toifl, Pavan Kumar Hanumolu. isscc 2011: 152-154 [doi]

A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data RecoveryWenjing Yin, Rajesh Inti, Amr Elshazly, Mrunmay Talegaonkar, Brian Young, Pavan Kumar Hanumolu. jssc, 46(12):3163-3173, 2011. [doi]

A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth TrackingWenjing Yin, Rajesh Inti, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu. jssc, 46(8):1870-1880, 2011. [doi]

2010

A 2.4ps resolution 2.1mW second-order noise-shaped time-to-digital converter with 3.2ns range in 1MHz bandwidthBrian Young, Sunwoo Kwon, Amr Elshazly, Pavan Kumar Hanumolu. cicc 2010: 1-4 [doi]

2004

2000

On-chip inductance modeling and analysisKaushik Gala, Vladimir Zolotov, Rajendran Panda, Brian Young, Junfeng Wang, David Blaauw. dac 2000: 63-68 [doi]

Model and analysis for combined package and on-chip power grid simulationRajendran Panda, David Blaauw, Rajat Chaudhry, Vladimir Zolotov, Brian Young, Ravi Ramaraju. islped 2000: 179-184 [doi]

1996

Effectiveness of Individual and Dyadic Training Protocols: The Influence of Trainee Interaction AnxietyWinfred Arthur, Brian Young, Jeffrey A. Jordan, Wayne L. Shebilske. hf, 38(1):79-86, 1996. [doi]

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Researchr

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Researchr

Publications by 'Brian Young'

Viewing Publication 1 - 28 from 28

2017

2015

2014

2013

2012

2011

2010

2004

2000

1996

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