Abstract is missing.
- New interfaces to the body through implantable-system integrationStephen Oesterle, Paul Gerrish, Peng Cong. 9-14 [doi]
- Game-changing opportunities for wireless personal healthcare and lifestyleJo De Boeck. 15-21 [doi]
- Eco-friendly semiconductor technologies for healthy livingOh-Hyun Kwon. 22-28 [doi]
- Beyond the horizon: The next 10x reduction in power - Challenges and solutionsJan M. Rabaey, Hugo De Man, Mark Horowitz, Takayasu Sakurai, Jack Sun, Dan Dobberpuhl, Kiyoo Itoh, Philippe Magarshack, Asad A. Abidi, Hermann Eul. 31 [doi]
- A 0.24nJ/b wireless body-area-network transceiver with scalable double-FSK modulationJoonsung Bae, Kiseok Song, Hyungwoo Lee, Hyunwoo Cho, Long Yan, Hoi-Jun Yoo. 34-36 [doi]
- A 75μW real-time scalable network controller and a 25μW ExG sensor IC for compact sleep-monitoring applicationsSeulki Lee, Long Yan, Taehwan Roh, Sunjoo Hong, Hoi-Jun Yoo. 36-38 [doi]
- A 3μW wirelessly powered CMOS glucose sensor for an active contact lensYu-Te Liao, Huanfen Yao, Babak A. Parviz, Brian P. Otis. 38-40 [doi]
- A 90nm CMOS SoC UWB pulse radar for respiratory rate monitoringDomenico Zito, Domenico Pepe, Martina Mincica, Fabio Zito. 40-41 [doi]
- A broadband THz imager in a low-cost CMOS technologyFranz Schuster, Hadley Videlier, Antoine Dupret, Dominique Coquillat, Maciej Sakowicz, Jean-Pierre Rostaing, Michaël Tchagaspanian, Benoît Giffard, Wojciech Knap. 42-43 [doi]
- A programmable implantable micro-stimulator SoC with wireless telemetry: Application in closed-loop endocardial stimulation for cardiac pacemakerShuenn-Yuh Lee, Yu-Cheng Su, Ming-Chun Liang, Jia-Hua Hong, Cheng-Han Hsieh, Chung-Min Yang, You-Yin Chen, Hsin-Yi Lai, Jou-Wei Lin, Qiang Fang. 44-45 [doi]
- A 660pW multi-stage temperature-compensated timer for ultra-low-power wireless sensor node synchronizationYoonmyung Lee, Bharan Giridhar, Zhiyoong Foo, Dennis Sylvester, David Blaauw. 46-48 [doi]
- A low-power fully integrated RF locked loop for Miniature Atomic ClockDavid Ruffieux, Matteo Contaldo, Jacques Haesler, Steve Lecomte. 48-50 [doi]
- Spur-free all-digital PLL in 65nm for mobile phonesRobert Bogdan Staszewski, Khurram Waheed, Sudheer Vemulapalli, Fikret Dulger, John L. Wallberg, Chih-Ming Hung, Oren Eliezer. 52-54 [doi]
- A 5.3GHz digital-to-time-converter-based fractional-N all-digital PLLNenad Pavlovic, Jos Bergervoet. 54-56 [doi]
- 2 3.5dB NF -5dBm P1dB fully differential CMOS push-pull LNA with integrated 34dBm T/R switch and ESD protectionChang-Tsung Fu, Hasnain Lakdawala, Stewart S. Taylor, Krishnamurthy Soumyanath. 56-58 [doi]
- A 65nm CMOS pulse-width-controlled driver with 8Vpp output voltage for switch-mode RF PAs up to 3.6GHzDavid A. Calvillo-Cortes, Mustafa Acar, Mark P. van der Heijden, Melina Apostolidou, Leo C. N. de Vreede, Domine Leenaerts, Jan Sonsky. 58-60 [doi]
- A low-power process-scalable superheterodyne receiver with integrated high-Q filtersAhmad Mirzaei, Hooman Darabi, David Murphy. 60-62 [doi]
- A 40nm CMOS highly linear 0.4-to-6GHz receiver resilient to 0dBm out-of-band blockersJonathan Borremans, Gunjan Mandal, Vito Giannini, Tomohiro Sano, Mark Ingels, Bob Verbruggen, Jan Craninckx. 62-64 [doi]
- A 1.0-to-4.0GHz 65nm CMOS four-element beamforming receiver using a switched-capacitor vector modulator with approximate sine weighting via charge redistributionMichiel C. M. Soer, Eric A. M. Klumperink, Bram Nauta, Frank E. van Vliet. 64-66 [doi]
- A harmonic rejection mixer robust to RF device mismatchesAslam A. Rafi, Alessandro Piovaccari, Peter J. Vancorenland, Tyson Tuttle. 66-68 [doi]
- A 5.2GHz microprocessor chip for the IBM zEnterprise™ systemJames D. Warnock, Yuen H. Chan, William V. Huott, Sean M. Carey, Michael F. Fee, Huajun Wen, M. J. Saccamango, Frank Malgioglio, Patrick J. Meaney, Donald W. Plass, Y. Chan, Mark D. Mayo, Guenter Mayer, Leon J. Sigal, David L. Rude, Robert M. Averill III, M. Wood, Thomas Strach, Howard H. Smith, Brian W. Curran, Eric M. Schwarz, Lee Eisen, Doug Malone, Steve Weitzel, Pak-kin Mak, Thomas J. McPherson, Charles F. Webb. 70-72 [doi]
- Dynamic hit logic with embedded 8Kb SRAM in 45nm SOI for the zEnterprise™ processorAntonio Pelella, Yuen H. Chan, Bargav Balakrishnan, Pradip Patel, Daniel Rodko, Richard E. Serton. 72-73 [doi]
- ® enterprise processorShankar Sawant, Utpal Desai, Gururaj Shamanna, Lokesh Sharma, Mandar Ranade, Anil Agarwal, Sampath Dakshinamurthy, Rajagopal Narayanan. 74-75 [doi]
- Godson-3B: A 1GHz 40W 8-core 128GFLOPS processor in 65nm CMOSWeiwu Hu, Ru Wang, Yunji Chen, Bao-Xia Fan, Shi-Qiang Zhong, Xiang Gao, Zichu Qi, Xu Yang. 76-78 [doi]
- Design solutions for the Bulldozer 32nm SOI 2-core processor module in an 8-core CPUTimothy Fischer, Srikanth Arekapudi, Eric Busta, Carl Dietz, Michael Golden, Scott Hilker, Aaron Horiuchi, Kevin A. Hurd, Dave Johnson, Hugh McIntyre, Samuel Naffziger, James Vinh, Jonathan White, Kathryn Wilcox. 78-80 [doi]
- 40-Entry unified out-of-order scheduler and integer execution unit for the AMD Bulldozer x86-64 coreMichael Golden, Srikanth Arekapudi, James Vinh. 80-82 [doi]
- Clock generation for a 32nm server processor with scalable coresShenggao Li, Ashwin Krishnakumar, Edward Helder, Roan Nicholson, Vivian Jia. 82-83 [doi]
- ® processor for mission-critical serversReid J. Riedlinger, Rohit Bhatia, Larry Biro, William J. Bowhill, Eric S. Fetzer, Paul E. Gronowski, Tom Grutkowski. 84-86 [doi]
- A 2.9-to-4.0GHz fractional-N digital PLL with bang-bang phase detector and 560fsrms integrated jitter at 4.5mW powerDavide Tasca, Marco Zanuso, Giovanni Marzin, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita. 88-90 [doi]
- An injection-locked ring PLL with self-aligned injection windowChe-Fu Liang, Keng-Jan Hsiao. 90-92 [doi]
- A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibrationAmr Elshazly, Rajesh Inti, Wenjing Yin, Brian Young, Pavan Kumar Hanumolu. 92-94 [doi]
- A 0.1-fref BW 1GHz fractional-N PLL with FIR-embedded phase-interpolator-based noise filteringDong-Woo Jee, Yunjae Suh, Hong June Park, Jae-Yoon Sim. 94-96 [doi]
- A scalable sub-1.2mW 300MHz-to-1.5GHz host-clock PLL for system-on-chip in 32nm CMOSHyung-Jin Lee, Alexandra M. Kern, Sami Hyvonen, Ian A. Young. 96-97 [doi]
- A 570fsrms integrated-jitter ring-VCO-based 1.21GHz PLL with hybrid loopAkihide Sai, Takafumi Yamaji, Tetsuro Itakura. 98-100 [doi]
- A rotary-traveling-wave-oscillator-based all-digital PLL with a 32-phase embedded phase-to-digital converter in 65nm CMOSKoji Takinami, Richard Strandberg, Paul C. P. Liang, Gregoìre Le Grand de Mercey, Tony Wong, Mahnaz Hassibi. 100-102 [doi]
- A low-power 3-axis digital-output MEMS gyroscope with single drive and multiplexed angular rate readoutLuciano Prandi, Carlo Caminada, Luca Coronato, Gabriele Cazzaniga, Fabio Biganzoli, Riccardo Antonello, Roberto Oboe. 104-106 [doi]
- A 50mW CMOS wind sensor with ±4% speed and ±2° direction errorJianfeng Wu, Youngcheol Chae, Caspar P. L. van Vroonhoven, Kofi A. A. Makinwa. 106-108 [doi]
- A telemetric stress-mapping CMOS chip with 24 FET-based stress sensors for smart orthodontic bracketsMatthias Kuhl, Pascal Gieschke, Daniel Rossbach, Sascha Alexander Hilzensauer, Patrick Ruther, Oliver Paul, Yiannos Manoli. 108-110 [doi]
- A 21b ±40mV range read-out IC for bridge transducersRong Wu, Johan H. Huijsing, Kofi A. A. Makinwa. 110-112 [doi]
- A ±1.5% nonlinearity 0.1-to-100A shunt current sensor based on a 6kV isolated micro-transformer for electrical vehicles and home automationFrédéric Rothan, Hélène Lhermet, Brice Zongo, Cyril Condemine, Henri Sibuet, Patrick Mas, Miguel Debarnot. 112-114 [doi]
- -rms accurate thresholdBart Dierickx, Benoit Dupont, Arnaud Defernez, Nayera Ahmed. 114-116 [doi]
- A 1.32pW/frame•pixel 1.2V CMOS energy-harvesting and imaging (EHI) APS imagerSuat U. Ay. 116-118 [doi]
- 5μW-to-10mW input power range inductive boost converter for indoor photovoltaic energy harvesting with integrated maximum power point tracking algorithmYifeng Qiu, Chris van Liempd, Bert Op het Veld, Peter G. Blanken, Chris Van Hoof. 118-120 [doi]
- A self-supplied inertial piezoelectric energy harvester with power-management ICEthem Erkan Aktakka, Rebecca L. Peterson, Khalil Najafi. 120-121 [doi]
- A 216fps 4096×2160p 3DTV set-top box SoC for free-viewpoint 3DTV applicationsPei-Kuei Tsung, Pin-Chih Lin, Kuan-Yu Chen, Tzu-Der Chuang, Hsin-Jung Yang, Shao-Yi Chien, Li-Fu Ding, Wei-Yin Chen, Chih-Chi Cheng, Tung-Chien Chen, Liang-Gee Chen. 124-126 [doi]
- A highly parallel and scalable CABAC decoder for next generation video codingVivienne Sze, Anantha P. Chandrakasan. 126-128 [doi]
- A 275mW heterogeneous multimedia processor for IC-stacking on Si-interposerHyo-Eun Kim, Jae-Sung Yoon, Kyu-Dong Hwang, Young-Jun Kim, Jun-Seok Park, Lee-Sup Kim. 128-130 [doi]
- A 57mW embedded mixed-mode neuro-fuzzy accelerator for intelligent multi-core processorJinwook Oh, Junyoung Park, Gyeonghoon Kim, Seungjin Lee, Hoi-Jun Yoo. 130-132 [doi]
- A 28nm 0.6V low-power DSP for mobile applicationsGordon Gammie, Nathan Ickes, Mahmut E. Sinangil, Rahul Rithe, Jie Gu, Alice Wang, Hugh Mair, Satyendra Datla, Bing-Rong, Sushma Honnavara Prasad, Lam Ho, Greg Baldwin, Dennis Buss, Anantha P. Chandrakasan, Uming Ko. 132-134 [doi]
- A MIMO WiMAX SoC in 90nm CMOS for 300km/h mobilityGene C. H. Chuang, Pangan Ting, Jen-Yuan Hsu, Jiun-You Lai, Shun-Chang Lo, Ying-Chuan Hsiao, Tzi-Dar Chiueh. 134-136 [doi]
- A 70Mb/s -100.5dBm sensitivity 65nm LP MIMO chipset for WiMAX portable routerJyh-Shin Pan, Ming-Yang Chao, E. Yeh, Wen-Wei Yang, Ching-Wen Hsueh, Shyuan Liao, Jian-Bang Lin, Shun-an Yang, Chin-Tai Liu, Tsai-Pao Lee, Jin-Ru Chen, Chia-Hua Chou, Min Chen, Den-Kai Juang, Jen-Hao Yeh, Chieh-Wei Liao, Po-Hung Chen, Kaipon Kao, Chia-Hsin Wu, Wen-Tso Huang, Shih-Hsien Liao, Chih-Heng Shih, Chien-Hsun Tung, Yen-Po Lee. 136-138 [doi]
- A direct digital frequency synthesizer with minimized tuning latency of 12nsAlan Willson, Mukund Ojha, Shilpa Agarwal, Thriven Lai, Tzu-Chieh Kuo. 138-140 [doi]
- 11.3Gb/s CMOS SONET-compliant transceiver for both RZ and NRZ applicationsNamik Kocaman, Adesh Garg, Bharath Raghavan, Delong Cui, Anand Vasani, Keith Tang, Deyi Pi, Haitao Tong, Siavash Fallahi, Wei Zhang, Ullas Singh, Jun Cao, Bo Zhang, Afshin Momtaz. 142-144 [doi]
- A full-duplex 10GBase-T transmitter hybrid with SFDR >65dBc Over 1 to 400MHz in 40nm CMOSGaurav Chandra, Moshe Malkin. 144-146 [doi]
- A 40Gb/s TX and RX chip set in 65nm CMOSMing-Shuan Chen, Yu-Nan Shih, Chen-Lun Lin, Hao-Wei Hung, Jri Lee. 146-148 [doi]
- 10: 4 MUX and 4: 10 DEMUX gearbox LSI for 100-gigabit Ethernet linkGoichi Ono, Keiki Watanabe, Takashi Muto, Hiroki Yamashita, Koji Fukuda, Noboru Masuda, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Masayoshi Yagyu, Hidehiro Toyoda, Akihiro Kambe, Tatsuya Saito, Shinji Nishimura. 148-150 [doi]
- A 12.5+12.5Gb/s full-duplex plastic waveguide interconnectSatoshi Fukuda, Yasufumi Hino, Sho Ohashi, Takahiro Takeda, Satoru Shinke, Masahiro Uno, Kenji Komori, Yoshiyuki Akiyama, Kenichi Kawasaki, Ali Hajimiri. 150-152 [doi]
- A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOSRajesh Inti, Amr Elshazly, Brian Young, Wenjing Yin, Marcel A. Kossel, Thomas Toifl, Pavan Kumar Hanumolu. 152-154 [doi]
- A 1-to-6Gb/s phase-interpolator-based burst-mode CDR in 65nm CMOSBehrooz Abiri, Ravi Shivnaraine, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune. 154-156 [doi]
- A 14Gb/s high-swing thin-oxide device SST TX in 45nm CMOS SOIChristian Menolfi, Thomas Toifl, Michael Ruegg, Matthias Braendli, Peter Buchmann, Marcel A. Kossel, Thomas Morf. 156-158 [doi]
- A 60GHz 16QAM/8PSK/QPSK/BPSK direct-conversion transceiver for IEEE 802.15.3cKenichi Okada, Kota Matsushita, Keigo Bunsen, Rui Murakami, Ahmed Musa, Takahiro Sato, Hiroki Asada, Naoki Takayama, Ning Li, Shogo Ito, Win Chaivipas, Ryo Minami, Akira Matsuzawa. 160-162 [doi]
- A 65nm CMOS fully integrated transceiver module for 60GHz wireless HD applicationsAlexandre Siligaris, Olivier Richard, Baudouin Martineau, Christopher Mounet, Fabrice Chaix, Romain Ferragut, Cedric Dehos, Jérôme Lanteri, Laurent Dussopt, Silas D. Yamamoto, Romain Pilard, Pierre Busson, Andreia Cathelin, Didier Belot, Pierre Vincent. 162-164 [doi]
- A 60GHz CMOS phased-array transceiver pair for multi-Gb/s wireless communicationsSohrab Emami, Robert F. Wiser, Ershad Ali, Mark G. Forbes, Michael Q. Gordon, Xiang Guan, Steve Lo, Patrick T. McElwee, James Parker, Jon R. Tani, Jeffrey M. Gilbert, Chinh H. Doan. 164-166 [doi]
- A 65nm CMOS 4-element Sub-34mW/element 60GHz phased-array transceiverMaryam Tabesh, Jiashu Chen, Cristian Marcu, Lingkai Kong, Shinwon Kang, Elad Alon, Ali M. Niknejad. 166-168 [doi]
- An 87GHz QPSK transceiver with costas-loop carrier recovery in 65nm CMOSShih-Jou Huang, Yu-Ching Yeh, Huaide Wang, Pang-Ning Chen, Jri Lee. 168-170 [doi]
- A 65nm dual-band 3-stream 802.11n MIMO WLAN SoCShahram Abdollahi-Alibeik, David Weber, Hakan Dogan, William W. Si, Burcin Baytekin, Abbas Komijani, Richard Chang, Babak Vakili-Amini, MeeLan Lee, Haitao Gan, Yashar Rajavi, Hirad Samavati, Brian Kaczynski, Sang Min Lee, Sotirios Limotyrakis, Hyunsik Park, Phoebe Chen, Paul Park, Mike Shuo-Wei Chen, Andrew Chang, Yangjin Oh, Jerry Jian-Ming Yang, Eric Chien-Chih Lin, Lalitkumar Nathawad, Keith Onodera, Manolis Terrovitis, Sunetra Mendis, Kai Shi, Srenik Mehta, Masoud Zargari, David Su. 170-172 [doi]
- 2 4dB-NF unified receiver front-end for full-band mobile TV in 65nm CMOSPui-In Mak, Rui Paulo Martins. 172-174 [doi]
- An all-digital 8-DPSK polar transmitter with second-order approximation scheme and phase rotation-constant digital PA for bluetooth EDR in 65nm CMOSHiroyuki Kobayashi, Shouhei Kousai, Yoshiaki Yoshihara, Mototsugu Hamada. 174-176 [doi]
- A digital-intensive receiver front-end using VCO-based ADC with an embedded 2nd-Order anti-aliasing Sinc filter in 90nm CMOSJaewook Kim, Wonsik Yu, Hyun-Kyu Yu, SeongHwan Cho. 176-178 [doi]
- A 480mW 2.6GS/s 10b 65nm CMOS time-interleaved ADC with 48.5dB SNDR up to NyquistKonstantinos Doris, Erwin Janssen, Claudio Nani, Athon Zanikopoulos, Gerard Van der Weide. 180-182 [doi]
- A 12b 1GS/s SiGe BiCMOS two-way time-interleaved pipeline ADCRobert Payne, Charles Sestok, William Bright, Manar El-Chammas, Marco Corsi, David Smith, Noam Tal. 182-184 [doi]
- An 800MS/s dual-residue pipeline ADC in 40nm CMOSJan Mulder, Frank M. L. van der Goes, Davide Vecchi, Jan R. Westra, Emre Ayranci, Christopher M. Ward, Jiansong Wan, Klaas Bult. 184-186 [doi]
- A 16b 80MS/s 100mW 77.6dB SNR CMOS pipeline ADCJ. Brunsilius, Eric Siragusa, Steve Kosic, Frank Murden, Ege Yetis, Binh Luu, Jeff Bray, Phil Brown, Allen Barlow. 186-188 [doi]
- 2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOSHe Gong Wei, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti. 188-190 [doi]
- A resolution-reconfigurable 5-to-10b 0.4-to-1V power scalable SAR ADCMarcus Yip, Anantha P. Chandrakasan. 190-192 [doi]
- A 12b 1.25GS/s DAC in 90nm CMOS with >70dB SFDR up to 500MHzWei-Hsin Tseng, Chi-Wei Fan, Jieh-Tsorng Wu. 192-194 [doi]
- A 56GS/S 6b DAC in 65nm CMOS with 256×6b memoryYuriy M. Greshishchev, Daniel Pollex, Shing-Chi Wang, Marinette Besson, Philip Flemeke, Stefan Szilagyi, Jorge Aguirre, Chris Falt, Naim Ben Hamida, Robert Gibbins, Peter Schvan. 194-196 [doi]
- 2 64Gb MLC NAND flash memory in 24nm CMOS technologyKoichi Fukuda, Yoshihisa Watanabe, Eiichi Makino, Koichi Kawakami, Jumpei Sato, Teruo Takagiwa, Naoaki Kanagawa, Hitoshi Shiga, Naoya Tokiwa, Yoshihiko Shindo, Toshiaki Edahiro, Takeshi Ogawa, Makoto Iwai, Osamu Nagao, Junji Musha, Takatoshi Minamoto, Kosuke Yanagidaira, Yuya Suzuki, Dai Nakamura, Yoshikazu Hosomura, Hiromitsu Komai, Yuka Furuta, Mai Muramoto, Rieko Tanaka, Go Shikata, Ayako Yuminaka, Kiyofumi Sakurai, Manabu Sakai, Hong Ding, Mitsuyuki Watanabe, Yosuke Kato, Toru Miwa, Alex Mak, Masaru Nakamichi, Gertjan Hemink, Dana Lee, Masaaki Higashitani, Brian Murphy, Bo Lei, Yasuhiko Matsunaga, Kiyomi Naruke, Takahiko Hara. 198-199 [doi]
- A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capabilityShyh-Shyuan Sheu, Meng-Fan Chang, Ku-Feng Lin, Che-Wei Wu, Yu-Sheng Chen, Pi-Feng Chiu, Chia-Chen Kuo, Yih-Shan Yang, Pei-Chia Chiang, Wen-Pin Lin, Che-He Lin, Heng-Yuan Lee, Peiyi Gu, Sumin Wang, Frederick T. Chen, Keng-Li Su, Chen-Hsin Lien, Kuo-Hsing Cheng, Hsin-Tun Wu, Tzu-Kun Ku, Ming-Jer Kao, Ming-Jinn Tsai. 200-202 [doi]
- A 32Gb MLC NAND flash memory with Vth margin-expanding schemes in 26nm CMOSTae-Yun Kim, Sang-Don Lee, Jin-su Park, Ho-youb Cho, Byoung-sung You, Kwang-ho Baek, Jae-Ho Lee, Chang-won Yang, Misun Yun, Min-Su Kim, Jong Woo Kim, Eun-seong Jang, Hyun Chung, Sang-o Lim, Bong-Seok Han, Yo-Hwan Koh. 202-204 [doi]
- 95%-lower-BER 43%-lower-power intelligent solid-state drive (SSD) with asymmetric coding and stripe pattern elimination algorithmShuhei Tanakamaru, Chinglin Hung, Atsushi Esumi, Mitsuyoshi Ito, Kai Li, Ken Takeuchi. 204-206 [doi]
- An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memoryMeng-Fan Chang, Shin-Jang Shen, Chia-Chi Liu, Che-Wei Wu, Yu-Fan Lin, Shang-Chi Wu, Chia-En Huang, Han-Chao Lai, Ya-Chin King, Chorng-Jung Lin, Hung-Jen Liao, Yu-Der Chih, Hiroyuki Yamauchi. 206-208 [doi]
- A low-voltage 1Mb FeRAM in 0.13μm CMOS featuring time-to-digital sensing for expanded operating margin in scaled CMOSMasood Qazi, Michael Clinton, Steven Bartling, Anantha P. Chandrakasan. 208-210 [doi]
- A 4Mb conductive-bridge resistive memory with 2.3GB/s read-throughput and 216MB/s program-throughputWataru Otsuka, Koji Miyata, Makoto Kitagawa, Keiichi Tsutsui, Tomohito Tsushima, Hiroshi Yoshihara, Tomohiro Namise, Yasuhiro Terao, Kentaro Ogata. 210-211 [doi]
- A 7MB/s 64Gb 3-bit/cell DDR NAND flash memory in 20nm-node technologyKi Tae Park, Ohsuk Kwon, Sangyong Yoon, Myung-Hoon Choi, In-Mo Kim, Bo-Geun Kim, Min-Seok Kim, Yoon-Hee Choi, Seung-Hwan Shin, Youngson Song, Joo-Yong Park, Jae-Eun Lee, Chang-Gyu Eun, Ho Chul Lee, Hyeong-Jun Kim, Jun-Hee Lee, Jong-Young Kim, Tae-Min Kweon, Hyun-Jun Yoon, Taehyun Kim, Dong-Kyo Shim, Jongsun Sel, Ji-Yeon Shin, Pansuk Kwak, Jin-Man Han, Keon-Soo Kim, SungSoo Lee, Youngho Lim, Tae-Sung Jung. 212-213 [doi]
- A 95mV-startup step-up converter with Vth-tuned oscillator by fixed-charge programming and capacitor pass-on schemePo-Hung Chen, Koichi Ishida, Katsuyuki Ikeuchi, Xin Zhang, Kentaro Honda, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai. 216-218 [doi]
- 100V AC power meter system-on-a-film (SoF) integrating 20V organic CMOS digital and analog circuits with floating gate for process-variation compensation and 100V organic PMOS rectifierKoichi Ishida, Tsung-Ching Huang, Kentaro Honda, Tsuyoshi Sekitani, Hiroyoshi Nakajima, Hiroki Maeda, Makoto Takamiya, Takao Someya, Takayasu Sakurai. 218-220 [doi]
- Real-time current-waveform sensor with plugless energy harvesting from AC power lines for home/building energy-management systemsShingo Takahashi, Nobuhide Yoshida, Kenichi Maruhashi, Muneo Fukaishi. 220-222 [doi]
- A 3.9ns 8.9mW 4×4 silicon photonic switch hybrid integrated with CMOS driverAlexander Rylyakov, Clint Schow, Benjamin G. Lee, William M. J. Green, Joris Van Campenhout, Min Yang, Fuad E. Doany, Solomon Assefa, Christopher V. Jahnes, Jeffrey A. Kash, Yurii A. Vlasov. 222-224 [doi]
- A 820GHz SiGe chipset for terahertz active imaging applicationsErik Öjefors, Janus Grzyb, Yan Zhao, Bernd Heinemann, Bernd Tillack, Ullrich R. Pfeiffer. 224-226 [doi]
- A 130μA wake-up receiver SoC in 0.13μm CMOS for reducing standby power of an electric appliance controlled by an infrared remote controllerHiroaki Ishihara, Toshiyuki Umeda, Katsuya Ohno, Shigeyasu Iwata, Fumi Moritsuka, Tetsuro Itakura, Manabu Ishibe, Keijiro Hijikata, Yasunori Maki. 226-228 [doi]
- Programmable cell array using rewritable solid-electrolyte switch integrated in 90nm CMOSMakoto Miyamura, Shogo Nakaya, Munehiro Tada, Toshitsugu Sakamoto, Koichiro Okamoto, Naoki Banno, Shinji Ishida, Kimihiko Ito, Hiromitsu Hada, Noboru Sakimura, Tadahiko Sugibayashi, Masato Motomura. 228-229 [doi]
- 2 inductive power transfer for non-contact wafer-level testingAndrzej Radecki, Hayun Chung, Yoichi Yoshida, Noriyuki Miura, Tsunaaki Shidei, Hiroki Ishikuro, Tadahiro Kuroda. 230-232 [doi]
- GHz-range continuous-time programmable digital FIR with power dissipation that automatically adapts to signal activityMariya Kurchuk, Colin Weltin-Wu, Dominique Morche, Yannis P. Tsividis. 232-234 [doi]
- A simple LED lamp driver IC with intelligent power-factor correctionJong Tae Hwang, Kunhee Cho, Donghwan Kim, Minho Jung, Gyehyun Cho, Seunguk Yang. 236-238 [doi]
- A 1.2A buck-boost LED driver with 13% efficiency improvement using error-averaged SenseFET-based current sensingSachin Rao, Qadeer Khan, Sarvesh Bang, Damian Swank, Arun Rao, William McIntyre, Pavan Kumar Hanumolu. 238-240 [doi]
- Filterless integrated class-D audio amplifier achieving 0.0012% THD+N and 96dB PSRR when supplying 1.2WMykhaylo A. Teplechuk, Tony Gribben, Christophe Amadi. 240-242 [doi]
- A 5.9nV/√Hz chopper operational amplifier with 0.78μV maximum offset and 28.3nV/°C offset driftYoshinori Kusuda. 242-244 [doi]
- A current-feedback instrumentation amplifier with a gain error reduction loop and 0.06% untrimmed gain errorRong Wu, Johan H. Huijsing, Kofi A. A. Makinwa. 244-246 [doi]
- A 6.7nV/√Hz Sub-mHz-1/f-corner 14b analog-to-digital interface for rail-to-rail precision voltage sensingChinwuba D. Ezekwe, Johan P. Vanderhaegen, Xinyu Xing, Ganesh K. Balachandran. 246-248 [doi]
- A 36V JFET-input bipolar operational amplifier with 1μV/°C maximum offset drift and -126dB total harmonic distortionMartijn F. Snoeij, Mikhail V. Ivanov. 248-250 [doi]
- 13.8A 3.3V-supply 120mW differential ADC driver amplifier in 0.18μm SiGe BiCMOS with 108dBc IM3 at 100MHzGwilym F. Luff. 250-252 [doi]
- A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancementsHarold Pilo, Igor Arsovski, Kevin Batson, Geordie Braceras, John Gabric, Robert M. Houle, Steve Lamphier, Frank Pavlik, Adnan Seferagic, Liang-Yu Chen, Shang-Bin Ko, Carl Radens. 254-256 [doi]
- A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operationGary S. Ditlow, Robert K. Montoye, Salvatore N. Storino, Sherman M. Dance, Sebastian Ehrenreich, Bruce M. Fleischer, Thomas W. Fox, Kyle M. Holmes, Junichi Mihara, Yutaka Nakamura, Shohji Onishi, Robert Shearer, Dieter Wendel, Leland Chang. 256-258 [doi]
- An 8MB level-3 cache in 32nm SOI with column-select aliasingDon Weiss, Michael Dreesen, Michael Ciraula, Carson Henrion, Chris Helt, Ryan Freese, Tommy Miles, Anita Karegar, Russell Schreiber, Bryan Schneller, John Wuu. 258-260 [doi]
- A 28nm high-density 6T SRAM with optimized peripheral-assist circuits for operation down to 0.6VMahmut E. Sinangil, Hugh Mair, Anantha P. Chandrakasan. 260-262 [doi]
- A fully integrated multi-CPU, GPU and memory controller 32nm processorMarcelo Yuffe, Ernest Knoll, Moty Mehalel, Joseph Shor, Tsvika Kurts. 264-266 [doi]
- An 80Gb/s dependable communication SoC with PCI express I/F and 8 CPUsSugako Otani, Hiroyuki Kondo, Itaru Nonomura, Atsuyuki Ikeya, Minoru Uemura, Yasushi Hayakawa, Takeshi Oshita, Satoshi Kaneko, Katsushi Asahina, Kazutami Arimoto, Shin'ichi Miura, Toshihiro Hanawa, Taisuke Boku, Mitsuhisa Sato. 266-268 [doi]
- A fully-integrated 3-level DC/DC converter for nanosecond-scale DVS with fast shunt regulationWonyoung Kim, David M. Brooks, Gu-Yeon Wei. 268-270 [doi]
- A low-power integrated x86-64 and graphics processor for mobile computing devicesSrinivasa Rao Gutta, Denis Foley, Ajay Naini, Robert Wasmuth, Don Cherepacha. 270-272 [doi]
- A programmable adaptive phase-shifting PLL for clock data compensation under resonant supply noiseDong Jiao, Chris H. Kim. 272-274 [doi]
- A side-channel and fault-attack resistant AES circuit working on duplicated complemented valuesMarion Doulcier-Verdier, Jean-Max Dutertre, Jacques Fournier, Jean-Baptiste Rigaud, Bruno Robisson, Assia Tria. 274-276 [doi]
- A 21.7-to-27.8GHz 2.6-degrees-rms 40Mw frequency synthesizer in 45nm CMOS for mm-Wave communication applicationsJuan F. Osorio, Cicero S. Vaucher, Bill Huff, Edwin v. d. Heijden, Anton de Graauw. 278-280 [doi]
- A mm-Wave quadrature VCO based on magnetically coupled resonatorsUgo Decanis, Andrea Ghilioni, Enrico Monaco, Andrea Mazzanti, Francesco Svelto. 280-282 [doi]
- A 6.5mW inductorless CMOS frequency divider-by-4 operating up to 70GHzAndrea Ghilioni, Ugo Decanis, Enrico Monaco, Andrea Mazzanti, Francesco Svelto. 282-284 [doi]
- A 60GHz antenna-referenced frequency-locked loop in 0.13μm CMOS for wireless sensor networksKuo-Ken Huang, David D. Wentzloff. 284-286 [doi]
- A 220-to-275GHz traveling-wave frequency doubler with -6.6dBm Power at 244GHz in 65nm CMOSOmeed Momeni, Ehsan Afshari. 286-288 [doi]
- Distributed active radiation for THz signal generationKaushik Sengupta, Ali Hajimiri. 288-289 [doi]
- A 120GHz 10Gb/s phase-modulating transmitter in 65nm LP CMOSNoël Deferm, Patrick Reynaert. 290-292 [doi]
- A 1.5GHz-modulation-range 10ms-modulation-period 180kHzrms-frequency-error 26MHz-reference mixed-mode FMCW synthesizer for mm-wave radar applicationHiroki Sakurai, Yuka Kobayashi, Toshiya Mitomo, Osamu Watanabe, Shoji Otaka. 292-294 [doi]
- A short-range UWB impulse-radio CMOS sensor for human feature detectionTa-Shun Chu, Jonathan Roderick, SangHyun Chang, Timothy Mercer, Chenliang Du, Hossein Hashemi. 294-296 [doi]
- 183GHz 13.5mW/pixel CMOS regenerative receiver for mm-wave imaging applicationsAdrian Tang 0002, Mau-Chung Frank Chang. 296-298 [doi]
- A 160μW 8-channel active electrode system for EEG monitoringJiawei Xu, Refet Firat Yazicioglu, Pieter Harpe, Kofi A. A. Makinwa, Chris Van Hoof. 300-302 [doi]
- 2 5μW DC-coupled neural signal acquisition IC with 0.5V supplyRikky Muller, Simone Gambini, Jan M. Rabaey. 302-304 [doi]
- An AC-powered optical receiver consuming 270μW for transcutaneous 2Mb/s data transferSteffen Lange, Hongcheng Xu, Christian Lang, Holger Pless, Joachim Becker, Hans-Jürgen Tiedkte, Eckhard Hennig, Maurits Ortmanns. 304-306 [doi]
- 2 in 0.35μm HVCMOSKriangkrai Sooksood, Emilia Noorsal, Joachim Becker, Maurits Ortmanns. 306-308 [doi]
- A low noise current readout architecture for fluorescence detection in living subjectsRoxana T. Heitz, David B. Barkin, Thomas D. O'Sullivan, Natesh Parashurama, Sanjiv S. Gambhir, Bruce A. Wooley. 308-310 [doi]
- A cubic-millimeter energy-autonomous wireless intraocular pressure monitorGregory K. Chen, Hassan Ghaed, Razi-Ul Haque, Michael Wieckowski, Yejoong Kim, Gyouho Kim, David Fick, Daeyeon Kim, Mingoo Seok, Kensall Wise, David Blaauw, Dennis Sylvester. 310-312 [doi]
- A 160×128 single-photon image sensor with on-pixel 55ps 10b time-to-digital converterChockalingam Veerappan, Justin A. Richardson, Richard J. Walker, Day-Uei Li, Matthew W. Fishburn, Yuki Maruyama, David Stoppa, Fausto Borghetti, Marek Gersbach, Robert K. Henderson, Edoardo Charbon. 312-314 [doi]
- Bidirectional OLED microdisplay: Combining display and image sensor functionality into a monolithic CMOS chipBernd Richter, Uwe Vogel, Rigo Herold, Karsten Fehse, Stephan Brenner, Lars Kroker, Judith Baumgarten. 314-316 [doi]
- 2 9b switched-current DAC for AMOLED mobile display driversHyunsik Kim, Jinyong Jeon, Sungwoo Lee, Junhyeok Yang, Seung-Tak Ryu, Gyu-Hyeong Cho. 316-318 [doi]
- A 10b resistor-resistor-string DAC with current compensation for compact LCD driver ICsChih-Wen Lu, Ping-Yeh Yin, Ching-Min Hsiao, Mau-Chung Frank Chang. 318-320 [doi]
- An 8b organic microprocessor on plastic foilKris Myny, Erik van Veenendaal, Gerwin H. Gelinck, Jan Genoe, Wim Dehaene, Paul Heremans. 322-324 [doi]
- A 3.3V 6b 100kS/s current-steering D/A converter using organic thin-film transistors on glassTarek Zaki, Frederik Ante, Ute Zschieschang, Joerg Butschke, Florian Letzkus, Harald Richter, Hagen Klauk, Joachim N. Burghartz. 324-325 [doi]
- A 1V printed organic DRAM cell based on ion-gel gated transistors with a sub-10nW-per-cell Refresh PowerWei Zhang 0032, Mingjing Ha, Daniele Braga, Michael J. Renn, C. Daniel Frisbie, Chris H. Kim. 326-328 [doi]
- Fully printed organic CMOS technology on plastic substrates for digital and analog applicationsAnis Daami, Cécile Bory, Mohamed Benwadih, Stéphanie Jacob, Romain Gwoziecki, Isabelle Chartier, Romain Coppard, Christophe Serbutoviez, Lidia Maddiona, Enzo Fontana, Antonino Scuderi. 328-330 [doi]
- A voltage-scalable biomedical signal processor running ECG using 13pJ/cycle at 1MHz and 0.4VMaryam Ashouei, Jos Hulzink, Mario Konijnenburg, Jun Zhou, Filipa Duarte, Arjan Breeschoten, Jos Huisken, Jan Stuyt, Harmke de Groot, Francisco Barat, Johan David, Johan Van Ginderdeuren. 332-334 [doi]
- An 82μA/MHz microcontroller with embedded FeRAM for energy-harvesting applicationsMichael Zwerg, Adolf Baumann, Rüdiger Kuhn, Matthias Arnold, Ronald Nerlich, Marcus Herzog, Ralph Ledwa, Christian Sichert, Volker Rzehak, Priya Thanigai, Bjoern Oliver Eversmann. 334-336 [doi]
- Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codecJulien Le Coz, Philippe Flatresse, Sylvain Engels, Alexandre Valentian, Marc Belleville, Christine Raynaud, Damien Croain, Pascal Urard. 336-337 [doi]
- A 77% energy-saving 22-transistor single-phase-clocking D-flip-flop with adaptive-coupling configuration in 40nm CMOSChen Kong Teh, Tetsuya Fujita, Hiroyuki Hara, Mototsugu Hamada. 338-340 [doi]
- A 62mV 0.13μm CMOS standard-cell-based design technique using schmitt-trigger logicNiklas Lotze, Yiannos Manoli. 340-342 [doi]
- A 0.27V 30MHz 17.7nJ/transform 1024-pt complex FFT core with super-pipeliningMingoo Seok, Dongsuk Jeon, Chaitali Chakrabarti, David Blaauw, Dennis Sylvester. 342-344 [doi]
- A 4-channel 10.3Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channelYasuo Hidaka, Takeshi Horie, Yoichi Koyanagi, Takashi Miyoshi, Hideki Osone, Samir Parikh, Subodh M. Reddy, Toshiyuki Shibuya, Yasushi Umezawa, William W. Walker. 346-348 [doi]
- A 1.0625-to-14.025Gb/s multimedia transceiver with full-rate source-series-terminated transmit driver and floating-tap decision-feedback equalizer in 40nm CMOSShaolei Quan, Freeman Zhong, Wing Liu, Pervez M. Aziz, Tai Jing, Jen Dong, Chintan Desai, Hairong Gao, Monica Garcia, Gary Hom, Tony Huynh, Hiroshi Kimura, Ruchi Kothari, Lijun Li, Cathy Liu, Scott Lowrie, Kathy Ling, Amaresh V. Malipatil, Ram Narayan, Tom Prokop, Chaitanya Palusa, Anil Rajashekara, Ashutosh Sinha, Charlie Zhong, Eric Zhang. 348-350 [doi]
- Analog-DFE-based 16Gb/s SerDes in 40nm CMOS that operates across 34dB loss channels at Nyquist with a baud rate CDR and 1.2Vpp voltage-mode driverAndrew K. Joy, Hugh Mair, Hae-Chang Lee, Arnold Feldman, Clemenz Portmann, Neil Bulman, Eugenia Cordero Crespo, Peter Hearne, Patty Huang, Ben Kerr, Pulkit Khandelwal, Franz Kuhlmann, Shaun Lytollis, Joaquim Machado, Casey Morrison, Scott Morrison, Shahriar Rabii, Dushmantha Rajapaksha, Vishnu Ravinuthula, Giuseppe Surace. 350-351 [doi]
- An 8.4mW/Gb/s 4-lane 48Gb/s multi-standard-compliant transceiver in 40nm digital CMOS technologyMehrdad Ramezani, Mohamed Abdalla, Ayal Shoval, Marcus van Ierssel, Afshin Rezayee, Angus McLaren, Chris D. Holdenried, Jennifer Pham, Eric So, David Cassan, Saman Sadr. 352-354 [doi]
- A pattern-guided adaptive equalizer in 65nm CMOSShayan Shahramian, Clifford Ting, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune. 354-356 [doi]
- A 6Gb/s receiver with 32.7dB adaptive DFE-IIR equalizationYi-Chieh Huang, Shen-Iuan Liu. 356-358 [doi]
- A 5.4Gb/s adaptive equalizer using asynchronous-sampling histogramsWang-Soo Kim, Chang-Kyung Seong, Woo-Young Choi. 358-359 [doi]
- 2 3.5GHz spread-spectrum clock generator with memoryless Newton-Raphson modulation profile in 0.13μm CMOSSewook Hwang, Minyoung Song, Young-Ho Kwak, Inhwa Jung, Chulwoo Kim. 360-362 [doi]
- A SAW-less GSM/GPRS/EDGE receiver embedded in a 65nm CMOS SoCIvan Siu-Chuang Lu, Chi-Yao Yu, Yen-horng Chen, Lan-chou Cho, Chih-hao Eric Sun, Chih-Chun Tang, George Chien. 364-366 [doi]
- A 9-band WCDMA/EDGE transceiver supporting HSPA evolutionMagnus Nilsson, Sven Mattisson, Nikolaus Klemmer, Martin Anderson, Torkel Arnborg, Peter Caputa, Staffan Ek, Lin Fan, Henrik Fredriksson, Fabien Garrigues, Henrik Geis, Hans Hagberg, Joel Hedestig, Hu Huang, Yevgeniy Kagan, Niklas Karlsson, Henrik Kinzel, Thomas Mattsson, Thomas Mills, Fenghao Mu, Andreas Mårtensson, Lars Nicklasson, Filip Oredsson, Ufuk Ozdemir, Fitzgerald Sungkyung Park, Tony Pettersson, Tony Påhlsson, Markus Pålsson, Stephane Ramon, Magnus Sandgren, Per Sandrup, Anna-Karin Stenman, Roland Strandberg, Lars Sundström, Fredrik Tillman, Tobias Tired, Satish Uppathil, Joel Walukas, Eric Westesson, Xuhao Zhang, Pietro Andreani. 366-368 [doi]
- A 65nm CMOS SoC with embedded HSDPA/EDGE transceiver, digital baseband and multimedia processorAlberto Cicalini, Sankaran Aniruddhan, Rahul Apte, Frederic Bossu, Ojas Choksi, Dan Filipovic, Kunal Godbole, Tsai-Pi Hung, Christos Komninakis, David Maldonado, Chiewcharn Narathong, Babak Nejati, Deirdre O'Shea, Xiaohong Quan, Raj Rangarajan, Janakiram Sankaranarayanan, Andrew See, Ravi Sridhara, Bo Sun, Wenjun Su, Klaas van Zalinge, Gang Zhang, Kamal Sahota. 368-370 [doi]
- A receiver for WCDMA/EDGE mobile phones with inductorless front-end in 65nm CMOSFederico Beffa, Tze Yee Sin, Alexander Tanzil, David Ivory, Bernard Tenbroek, Jon Strange, Walid Ali-Ahmad. 370-372 [doi]
- A compact SAW-less multiband WCDMA/GPS receiver front-end with translational loop for input matchingXin He, Harish Kundur. 372-374 [doi]
- A multiband LTE SAW-less modulator with -160dBc/Hz RX-band noise in 40nm LP CMOSVito Giannini, Mark Ingels, Tomohiro Sano, Björn Debaillie, Jonathan Borremans, Jan Craninckx. 374-376 [doi]
- A fully digital multimode polar transmitter employing 17b RF DAC in 3G modeZdravko Boos, Andreas Menkhoff, Franz Kuttner, Markus Schimper, Jose Moreira, Hans Geltinger, Timo Gossmann, Peter Pfann, Alexander Belitzer, Thomas Bauernfeind. 376-378 [doi]
- A low-power wideband polar transmitter for 3G applicationsMichael Youssef, Alireza Zolfaghari, Hooman Darabi, Asad A. Abidi. 378-380 [doi]
- A fully integrated power-management solution for a 65nm CMOS cellular handset chipArnold James D'Souza, Ravpreet Singh, J. Raja Prabhu, Gajendranath Chowdary, Ankit Seedher, Shyam Somayajula, Nageswara Rao Nalam, Lionel Cimaz, Stephane Le Coq, Praveen Kallam, Siddharth Sundar, Shanfeng Cheng, Sanjay Tumati, Wenchang Huang. 382-384 [doi]
- A digitally controlled DC-DC converter for SoC in 28nm CMOSFranz Kuttner, Harun Habibovic, Thomas Hartig, Michael Fulde, Gernot Babin, Andreas Santner, Peter Bogner, Claus Kropf, Harald Riesslegger, Uwe Hodel. 384-385 [doi]
- 20μA to 100mA DC-DC converter with 2.8 to 4.2V battery supply for portable applications in 45nm CMOSSaurav Bandyopadhyay, Yogesh K. Ramadass, Anantha P. Chandrakasan. 386-388 [doi]
- A digitally controlled DC-DC buck converter with lossless load-current sensing and BIST functionalityTao Liu, Hyunsoo Yeom, Bert Vermeire, Philippe Adell, Bertan Bakkaloglu. 388-390 [doi]
- Zero-order control of boost DC-DC converter with transient enhancement using residual currentTae-Hwang Kong, Young-Jin Woo, Se-Won Wang, Sung-Wan Hong, Gyu-Hyeong Cho. 390-392 [doi]
- Robust and efficient synchronous buck converter with near-optimal dead-time controlSungwoo Lee, Seungchul Jung, Jin Huh, Changbyung Park, Chun-Taek Rim, Gyu-Hyeong Cho. 392-394 [doi]
- A 90% peak efficiency single-inductor dual-output buck-boost converter with extended-PWM controlWeiwei Xu, Ye Li, Zhiliang Hong, Dirk Killat. 394-396 [doi]
- Spurious-noise-free buck regulator for direct powering of analog/RF loads using PWM control with random frequency hopping and random phase choppingChengwu Tao, Ayman A. Fayed. 396-398 [doi]
- An 80μVrms-temporal-noise 82dB-dynamic-range CMOS Image Sensor with a 13-to-19b variable-resolution column-parallel folding-integration/cyclic ADCMin-Woong Seo, Sungho Suh, Tetsuya Iida, Hiroshi Watanabe, Taishi Takasawa, Tomoyuki Akahori, Keigo Isobe, Takashi Watanabe, Shinya Itoh, Shoji Kawahito. 400-402 [doi]
- A sub-electron readout noise CMOS image sensor with pixel-level open-loop voltage amplificationChristian Lotto, Peter Seitz, Thomas Baechler. 402-404 [doi]
- A 16 Mfps 165kpixel backside-illuminated CCDTakeharu G. Etoh, Dung H. Nguyen, Son V. T. Dao, Cuong L. Vo, Masatoshi Tanaka, Masatoshi Takehara, Tomoo Okinaka, Harry van Kuijk, Wilco Klaassens, Jan T. Bosiers, Michael Lesser, David Ouellette, Hirotaka Maruyama, Tetsuya Hayashida, Toshiki Arai. 406-408 [doi]
- A 300mm wafer-size CMOS image sensor with in-pixel voltage-gain amplifier and column-level differential readout circuitryYuichiro Yamashita, Hidekazu Takahashi, Shin Kikuchi, Keisuke Ota, Masato Fujita, Satoshi Hirayama, Taikan Kanou, Sakae Hashimoto, Genzo Momma, Shunsuke Inoue. 408-410 [doi]
- A 128×96 pixel event-driven phase-domain ΔΣ-based fully digital 3D camera in 0.13μm CMOS imaging technologyRichard J. Walker, Justin A. Richardson, Robert K. Henderson. 410-412 [doi]
- An angle-sensitive CMOS imager for single-sensor 3D photographyAlbert Wang, Patrick R. Gill, Alyosha Molnar. 412-414 [doi]
- A 1/13-inch 30fps VGA SoC CMOS image sensor with shared reset and transfer-gate pixel controlRobert Johansson, A. Storm, C. Stephansen, S. Eikedal, T. Willassen, S. Skaug, T. Martinussen, D. Whittlesea, G. Ali, John Ladd, X. Li, S. Johnson, V. Rajasekaran, Y. Lee, J. Bai, M. Flores, G. Davies, H. Samiy, A. Hanvey, D. Perks. 414-415 [doi]
- A 1/2.33-inch 14.6M 1.4μm-pixel backside-illuminated CMOS image sensor with floating diffusion boostingSangjoo Lee, Kyungho Lee, JongEun Park, Hyungjun Han, Younghwan Park, Taesub Jung, Youngheup Jang, Bumsuk Kim, Yitae Kim, Shay Hamami, Uzi Hizi, Mickey Bahar, Changrok Moon, JungChak Ahn, Duckhyung Lee, Hiroshige Goto, Yun-Tae Lee. 416-418 [doi]
- An APS-C format 14b digital CMOS image sensor with a dynamic response pixelDan Pates, Jeong-Ho Lyu, Shinji Osawa, Isao Takayanagi, Toshiaki Sato, Tim Bales, Katsuyuki Kawamura, Eduard Pages, Shinichiro Matsuo, Tetsuji Kawaguchi, Tadashi Sugiki, Norio Yoshimura, Junichi Nakamura, John Ladd, Zhiping Yin, Russell Iimura, Xiaofeng Fan, Scott Johnson, Aditya Rayankula, Rick Mauritzson, Gennadiy Agranov. 418-420 [doi]
- A 17.7Mpixel 120fps CMOS image sensor with 34.8Gb/s readoutTakayuki Toyama, Koji Mishina, Koji Tsuchiya, Tatsuya Ichikawa, Hiroyuki Iwaki, Yuji Gendai, Hirotaka Murakami, Kenichi Takamiya, Hiroshi Shiroshita, Yoshinori Muramatsu, Toshihiro Furusawa. 420-422 [doi]
- A 40nm wideband direct-conversion transmitter with sub-sampling-based output power, LO feedthrough and I/Q imbalance calibrationEmanuele Lopelli, Silvian Spiridon, Johan van der Tang. 424-426 [doi]
- A flip-chip-packaged 1.8V 28dBm class-AB power amplifier with shielded concentric transformers in 32nm SoC CMOSYulin Tan, Hongtao Xu, Mohammed A. El-Tanani, Stewart S. Taylor, Hasnain Lakdawala. 426-428 [doi]
- A switched-capacitor power amplifier for EER/polar transmittersSang-Min Yoo, Jeffrey S. Walling, Eum Chan Woo, David J. Allstot. 428-430 [doi]
- An EDGE/GSM quad-band CMOS power amplifierWoonyun Kim, Ki Seok Yang, Jeonghu Han, Jaejoon Chang, Chang-Ho Lee. 430-432 [doi]
- A compact 1V 18.6dBm 60GHz power amplifier in 65nm CMOSJiashu Chen, Ali M. Niknejad. 432-433 [doi]
- A 5Gb/s adaptive DFE for 2x blind ADC-based CDR in 65nm CMOSBehrooz Abiri, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune. 436-438 [doi]
- A 0.5-to-2.5Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error toleranceRajesh Inti, Wenjing Yin, Amr Elshazly, Naga Sasidhar, Pavan Kumar Hanumolu. 438-450 [doi]
- A TDC-less 7mW 2.5Gb/s digital CDR with linear loop dynamics and offset-free data recoveryWenjing Yin, Rajesh Inti, Amr Elshazly, Pavan Kumar Hanumolu. 440-442 [doi]
- A digital wideband CDR with ±15.6kppm frequency tracking at 8Gb/s in 40nm CMOSHui Pan, Magesh Valliappan, Wei Zhang, Kambiz Vakilian, Seong Ho Lee, Hamid Hatamkhani, Mario Caresosa, Karo Khanoyan, Haitao Tong, Duke Tran, Anthony Brewster, Ichiro Fujimori. 442-444 [doi]
- A 20Gb/s digitally adaptive equalizer/DFE with blind samplingYu-Ming Ying, Shen-Iuan Liu. 444-446 [doi]
- A 15Gb/s 0.5mW/Gb/s 2-tap DFE receiver with far-end crosstalk cancellationMeisam Honarvar Nazari, Azita Emami-Neyestanak. 446-448 [doi]
- A 10Gb/s half-UI IIR-tap transmitter in 40nm CMOSHalil Cirit, Marc J. Loinaz. 448-450 [doi]
- A 13.8mW 3.0Gb/s clock-embedded video interface with DLL-based data-recovery circuitSungchun Jang, Heesoo Song, Seokmin Ye, Deog Kyoon Jeong. 450-452 [doi]
- A 7.9μW remotely powered addressed sensor node using EPC HF and UHF RFID technology with -10.3dBm sensitivityHannes Reinisch, Martin Wiessflecker, Stefan Gruber, Hartwig Unterassinger, Günter Hofer, Michael Klamminger, Wolfgang Pribyl, Gerald Holweg. 454-456 [doi]
- An isolator-less CMOS RF front-end for UHF mobile RFID readerEun Hee Kim, Kwyro Lee, Jinho Ko. 456-458 [doi]
- A 2.4GHz ULP OOK single-chip transceiver for healthcare applicationsMaja Vidojkovic, Xiongchuan Huang, Pieter Harpe, Simonetta Rampu, Cui Zhou, Li Huang, Koji Imamura, Ben Busze, Frank Bouwens, Mario Konijnenburg, Juan Santana, Arjan Breeschoten, Jos Huisken, Guido Dolmans, Harmke de Groot. 458-460 [doi]
- A 120μW MICS/ISM-band FSK receiver with a 44μW low-power mode based on injection-locking and 9x frequency multiplicationJagdish Nayayan Pandey, Jianlei Shi, Brian P. Otis. 460-462 [doi]
- A GPS/Galileo SoC with adaptive in-band blocker cancellation in 65nm CMOSChia-Hsin Wu, Wen-Chieh Tsai, Chun-Geik Tan, Chun-Nan Chen, Kuan-I. Li, Jui-Lin Hsu, Chi-Lun Lo, Hsin-Hua Chen, Sheng-Yuan Su, Kun-Tso Chen, Min Chen, Osama Shana'a, Shu-Hung Chou, George Chien. 462-464 [doi]
- A 0.05-to-10GHz 19-to-22GHz and 38-to-44GHz SDR frequency synthesizer in 0.13μm CMOSSujiang Rong, Howard C. Luong. 464-466 [doi]
- A 4.6GHz MDLL with -46dBc reference spur and aperture position tuningTamer A. Ali, Amr Amin Hafez, Robert J. Drost, Ronald Ho, Chih-Kong Ken Yang. 466-468 [doi]
- A 4GHz CT ΔΣ ADC with 70dB DR and -74dBFS THD in 125MHz BWMuhammed Bolatkale, Lucien J. Breems, Robert Rutten, Kofi A. A. Makinwa. 470-472 [doi]
- An 8mW 50MS/s CT ΔΣ modulator with 81dB SFDR and digital background DAC linearizationJohn G. Kauffman, Pascal Witte, Joachim Becker, Maurits Ortmanns. 472-474 [doi]
- A third-order DT ΔΣ modulator using noise-shaped bidirectional single-slope quantizerNima Maghari, Un-Ku Moon. 474-476 [doi]
- A 250mV 7.5μW 61dB SNDR CMOS SC ΔΣ modulator using a near-threshold-voltage-biased CMOS inverter techniqueFridolin Michel, Michiel Steyaert. 476-478 [doi]
- A 84dB SNDR 100kHz bandwidth low-power single op-amp third-order ΔΣ modulator consuming 140μWAldo Pena-Perez, Edoardo Bonizzoni, Franco Maloberti. 478-480 [doi]
- A 1.7mW 11b 1-1-1 MASH ΔΣ time-to-digital converterYing Cao, Paul Leroux, Wouter De Cock, Michiel Steyaert. 480-482 [doi]
- A 120dB-SNR 100dB-THD+N 21.5mW/channel multibit CT ΔΣ DACAbhishek Bandyopadhyay, Michael Determan, Sejun Kim, Khiem Nguyen. 482-483 [doi]
- A 108dB-DR 120dB-THD and 0.5Vrms output audio DAC with inter-symbol-interference-shaping algorithm in 45nm CMOSLars Risbo, Rahmi Hezar, Burak Kelleci, Halil Kiper, Mounir Fares. 484-485 [doi]
- An 8.4Gb/s 2.5pJ/b mobile memory I/O interface using simultaneous bidirectional Dual (Base+RF) band signalingGyungsu Byun, Yanghyo Kim, Jongsun Kim, Sai-Wang Tam, Hsieh-Hung Hsieh, P. Y. Wu, Chewnpu Jou, Jason Cong, Glenn Reinman, Mau-Chung Frank Chang. 488-490 [doi]
- 2 0.9pJ/b/chip 1coil/channel ThruChip interface with coupled-resonator-based CDR for NAND Flash memory stackingNoriyuki Miura, Yasuhiro Take, Mitsuko Saito, Yoichi Yoshida, Tadahiro Kuroda. 490-492 [doi]
- A 12Gb/s non-contact interface with coupled transmission linesTsutomu Takeya, Lan Nan, Shinya Nakano, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda. 492-494 [doi]
- A 4.8Gb/s impedance-matched bidirectional multi-drop transceiver for high-capacity memory interfaceWoo-Yeol Shin, Gi-Moon Hong, Hyongmin Lee, Jae-Duk Han, Sunkwon Kim, Kyu-Sang Park, Dong-Hyuk Lim, Jung-Hoon Chun, Deog Kyoon Jeong, Suhwan Kim. 494-496 [doi]
- A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stackingJung Sik Kim, Chi Sung Oh, Hocheol Lee, Donghyuk Lee, Hyong-Ryol Hwang, Sooman Hwang, Byongwook Na, Joungwook Moon, Jin Guk Kim, Hanna Park, Jang-Woo Ryu, Kiwon Park, Sang-Kyu Kang, So-Young Kim, Hoyoung Kim, Jong-Min Bang, Hyunyoon Cho, Minsoo Jang, Cheolmin Han, Jung-Bae Lee, Kyehyun Kyung, Joo-Sun Choi, Young-Hyun Jun. 496-498 [doi]
- A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BWSeung-Jun Bae, Young-Soo Sohn, Tae-young Oh, Si-Hong Kim, Yun-Seok Yang, Dae-Hyun Kim, Sang-Hyup Kwak, Ho-Seok Seol, Chang-Ho Shin, Min-Sang Park, Gong-Heom Han, Byeong-Cheol Kim, Yong-Ki Cho, Hye-Ran Kim, Su-Yeon Doo, Young-Sik Kim, Dong-Seok Kang, Young-Ryeol Choi, Sam-Young Bang, Sun Young Park, Yong-Jae Shin, Gil-Shin Moon, Cheol-Goo Park, Woo-Seop Kim, Hyang-Ja Yang, Jeong-Don Lim, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun. 498-500 [doi]
- A 58nm 1.8V 1Gb PRAM with 6.4MB/s program BWHoeju Chung, Byung-Hoon Jeong, ByungJun Min, Youngdon Choi, Beak-Hyung Cho, Junho Shin, Jinyoung Kim, Jung Sunwoo, Joon-min Park, Qi Wang, Yong-jun Lee, Sooho Cha, Dukmin Kwon, Sangtae Kim, Sunghoon Kim, Yoohwan Rho, Mu-Hui Park, Jaewhan Kim, Ickhyun Song, Sunghyun Jun, Jaewook Lee, KiSeung Kim, Ki Won Lim, Won-ryul Chung, ChangHan Choi, HoGeun Cho, Inchul Shin, Woochul Jun, Seokwon Hwang, Ki-Whan Song, KwangJin Lee, Sang-whan Chang, Woo-Yeong Cho, Jei-Hwan Yoo, Young-Hyun Jun. 500-502 [doi]
- A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technologyHyun-Woo Lee, Ki-Han Kim, Young-Kyoung Choi, Ju-Hwan Shon, Nak-Kyu Park, Kwan-Weon Kim, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung. 502-504 [doi]
- An embedded DRAM technology for high-performance NAND flash memoriesDaisaburo Takashima, Mitsuhiro Noguchi, Noboru Shibata, Kazushige Kanda, Hiroshi Sukegawa, Shuso Fujii. 504-505 [doi]
- A 700MHz 2T1C embedded DRAM macro in a generic logic process with no boosted suppliesKi Chul Chun, Wei Zhang 0032, Pulkit Jain, Chris H. Kim. 506-507 [doi]
- Advanced transmitters for wireless infrastructureGabriele Manganaro, Domine Leenaerts, Francesco Dantoni, Andrea Baschirotto, Robert Bogdan Staszewski, Nikolaus Klemmer, Seongchol Hong. 512-513 [doi]
- Ultra-low voltage VLSIs for energy efficient systemsKen Takeuchi, Ken Chang, Kevin Zhang, Tadaaki Yamauchi, Roberto Gastaldi. 514-515 [doi]
- Towards personalized medicine and monitoring for healthy livingChristian Enz, Andreia Cathelin, Maysam Ghovanloo, Stefan Heinen, Minkyu Je, David Scott. 516-517 [doi]
- Design of "green" high-performance processor circuitsTobias Noll, Raney Southerland, Vladimir Stojanovic, Sonia Leon, Lew Chua-Eoan, Alice Wang, Byeong-Gyu Nam, Masaya Sumita. 518-519 [doi]
- Image sensors for 3D captureJohannes Solhusvik, Albert Theuwissen, Sam Kavusi, Tetsuo Nomoto, Iliana Chen. 520-521 [doi]
- High-speed transceivers: Standards, challenges, and futureAli Sheikholeslami, Franz Dielacher, Miki Moyal, Jafar Savoj, John Stonick, Takuji Yamamoto. 522-523 [doi]
- Cellular and wireless LAN transceivers: From systems to circuit designJohn R. Long, Hooman Darabi, F. O. Eynde, Behzad Razavi, Robert Bogdan Staszewski. 524 [doi]
- Good, bad, ugly - 20 years of broadband evolution: What's next?Jerry Lin, Franz Dielacher, Jing-Hong Conan Zhan, Robert Payne. 525 [doi]
- 20-22nm technology options and design implicationsDon Draper. 526 [doi]
- Data converter breakthroughs in retrospectBoris Murmann, Venu Gopinathan. 528 [doi]
- Wireless sensor systems: Solution & technologyPascal Urard, Jun Ohta. 529 [doi]
- Future system and memory architectures: Transformations by technology and applicationsNicky Lu, Leland Chang, Daisaburo Takashima. 530 [doi]
- Body area network: Technology, solutions, and standardizationHoi-Jun Yoo, Alison Burdett. 531 [doi]
- Gb/s+ portable wireless communicationsDidier Belot, George Chien. 532 [doi]
- Technologies for smart grid and smart meterJed Hurwitz, Wing-Hung Ki. 533 [doi]