Takahiko Hara - researchr alias

researchr

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Viewing Publication 1 - 12 from 12

2013

2012

2011

2009

2006

1997

Flexible test mode approach for 256-Mb DRAMToshiaki Kirihata, Hing Wong, John K. DeBrosse, Yohji Watanabe, Takahiko Hara, Munehiro Yoshida, Matthew R. Wordeman, Shuso Fujii, Yoshiaki Asao, Bo Krsnik. jssc, 32(10):1525-1534, 1997. [doi]

1993

Low-power on-chip supply voltage conversion scheme for ultrahigh-density DRAMsDaisaburo Takashima, Shigeyoshi Watanabe, Tsuneaki Fuse, Kazumasa Sunouchi, Takahiko Hara. jssc, 28(4):504-509, April 1993. [doi]

BiCMOS circuit technology for high-speed DRAMsShigeyoshi Watanabe, Koji Sakui, Tsuneaki Fuse, Takahiko Hara, Seiichi Aritome, Katsuhiko Hieda. jssc, 28(1):4-9, January 1993. [doi]

1991

A 17-ns 4-Mb CMOS DRAMTakeshi Nagai, Kenji Numata, Masaki Ogihara, Mitsuru Shimizu, Kimimasa Imai, Takahiko Hara, Munehiro Yoshida, Yoshikazu Saito, Yoshiaki Asao, Shizuo Sawada, Syuso Fujii. jssc, 26(11):1538-1543, November 1991. [doi]

1989

A 45-ns 16-Mbit DRAM with triple-well structureSyuso Fujii, Masaki Ogihara, Mitsuru Shimizu, Munehiro Yoshida, Kenji Numata, Takahiko Hara, Shigeyoshi Watanabe, Shizuo Sawada, Tomohisa Mizuno, Junpei Kumagai, Susumu Yoshikawa, Sejii Kaki, Yoshikazu Saito, Hideaki Aochi, Takeshi Hamamoto, Koichi Toita. jssc, 24(5):1170-1175, October 1989. [doi]

New nibbled-page architecture for high-density DRAMsKenji Numata, Yukihito Oowaki, Yasuo Itoh, Takahiko Hara, Kenji Tsuchida, Masako Ohta, Shigyoshi Watanabe, Kazunori Ohuchi. jssc, 24(4):900-904, August 1989. [doi]

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