Daisaburo Takashima - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 29 from 29

2019

A 7T-SRAM With Data-Write Technique by Capacitive CouplingDaisaburo Takashima, Masato Endo, Kazuhiro Shimazaki, Manabu Sai, Masaaki Tanino. jssc, 54(2):596-605, 2019. [doi]

2015

Highly Reliable Reference Bitline Bias Designs for 64 Mb and 128 Mb Chain FeRAMsRyu Ogiwara, Daisaburo Takashima, Sumiko Doumae, Shinichiro Shiratake, Ryosuke Takizawa, Hidehiro Shiga. jssc, 50(5):1324-1331, 2015. [doi]

A 7T-SRAM with data-write technique by capacitive couplingDaisaburo Takashima, Masato Endo, Kazuhiro Shimazaki, Manabu Sai, Masaaki Tanino. asscc 2015: 1-4 [doi]

2012

Session 2 overview: High-bandwidth DRAM & PRAM: Memory subcommitteeJoo-Sun Choi, Daisaburo Takashima. isscc 2012: 36-37 [doi]

An Embedded DRAM Technology for High-Performance NAND Flash MemoriesDaisaburo Takashima, Mitsuhiro Noguchi, Noboru Shibata, Kazushige Kanda, Hiroshi Sukegawa, Shuso Fujii. jssc, 47(2):536-546, 2012. [doi]

2011

Future system and memory architectures: Transformations by technology and applicationsNicky Lu, Leland Chang, Daisaburo Takashima. isscc 2011: 530 [doi]

A 100 MHz Ladder FeRAM Design With Capacitance-Coupled-Bitline (CCB) CellDaisaburo Takashima, Yasushi Nagadomi, Tohru Ozaki. jssc, 46(3):681-689, 2011. [doi]

A 128 Mb Chain FeRAM and System Design for HDD Application and Enhanced HDD PerformanceDaisaburo Takashima, Yasushi Nagadomi, Kosuke Hatsuda, Yohji Watanabe, Shuso Fujii. jssc, 46(2):530-536, 2011. [doi]

An embedded DRAM technology for high-performance NAND flash memoriesDaisaburo Takashima, Mitsuhiro Noguchi, Noboru Shibata, Kazushige Kanda, Hiroshi Sukegawa, Shuso Fujii. isscc 2011: 504-505 [doi]

2010

A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s Burst ModeKatsuhiko Hoya, Daisaburo Takashima, Shinichiro Shiratake, Ryu Ogiwara, T. Miyakawa, H. Shiga, S. M. Doumae, S. Ohtsuki, Y. Kumura, S. Shuto, T. Ozaki, K. Yamakawa, I. Kunishima, A. Nitayama, S. Fujii. tvlsi, 18(12):1745-1752, 2010. [doi]

2009

2006

A 64Mb Chain FeRAM with Quad-BL Architecture and 200MB/s Burst ModeKatsuhiko Hoya, Daisaburo Takashima, Shinichiro Shiratake, Ryu Ogiwara, Tadashi Miyakawa, Hidehiro Shiga, S. M. Doumae, S. Ohtsuki, Yoshinori Kumura, Susumu Shuto, Tohru Ozaki, Koji Yamakawa, Iwao Kunishima, Akihiro Nitayama, Shuso Fujii. isscc 2006: 459-466 [doi]

2003

2002

A cell transistor scalable DRAM array architectureDaisaburo Takashima, Hiroaki Nakano. jssc, 37(5):587-591, 2002. [doi]

2001

A 76-mm/sup 2/ 8-Mb chain ferroelectric memoryDaisaburo Takashima, Yoshiaki Takeuchi, Tadashi Miyakawa, Yasuo Itoh, Ryu Ogiwara, Masahiro Kamoshida, Katsuhiko Hoya, Sumiko Mano Doumae, Tohru Ozaki, Hiroyuki Kanaya, Koji Yamakawa, Iwao Kunishima, Yukihito Oowaki. jssc, 36(11):1713-1720, 2001. [doi]

1999

A sub-40-ns chain FRAM architecture with 7-ns cell-plate-line driveDaisaburo Takashima, Susumu Shuto, Iwao Kunishima, Hiroyuki Takenaka, Yukihito Oowaki, Shin'ichi Tanaka. jssc, 34(11):1557-1563, 1999. [doi]

1998

Noise suppression scheme for gigabit-scale and gigabyte/s data-rate LSI'sDaisaburo Takashima, Yukihito Oowaki, Shigeyoshi Watanabe, Kazunori Ohuchi. jssc, 33(2):260-267, 1998. [doi]

High-density chain ferroelectric random access memory (chain FRAM)Daisaburo Takashima, Iwao Kunishima. jssc, 33(5):787-792, 1998. [doi]

1997

A novel power-off mode for a battery-backup DRAMDaisaburo Takashima, Yukihito Oowaki. jssc, 32(1):86-91, 1997. [doi]

1994

Open/folded bit-line arrangement for ultra-high-density DRAM'sDaisaburo Takashima, Shigeyoshi Watanabe, Hiroaki Nakano, Yukihito Oowaki, Kazunori Ohuchi. jssc, 29(4):539-542, April 1994. [doi]

Standby/active mode logic for sub-1-V operating ULSI memoryDaisaburo Takashima, Shigeyoshi Watanabe, Hiroalu Nakano, Yukihito Oowaki, Kazunori Ohuchi, Hiroyuki Tango. jssc, 29(4):441-447, April 1994. [doi]

1993

1992

Word-line architecture for highly reliable 64-Mb DRAMDaisaburo Takashima, Yukihito Oowaki, Ryu Ogiwara, Yohji Watanabe, Kenji Tsuchida, Masako Ohta, Hiroaki Nakano, Shigeyoshi Watanabe, Kazunori Ohuchi. jssc, 27(4):603-609, April 1992. [doi]

1991

A 33-ns 64-Mb DRAMYukihito Oowaki, Kenji Tsuchida, Yohji Watanabe, Daisaburo Takashima, Masako Ohta, Hiroaki Nakano, Shigeyoshi Watanabe, Akihiro Nitayama, Fumio Horiguchi, Kazunori Ohuchi, Fujio Masuoka. jssc, 26(11):1498-1505, November 1991. [doi]

1990

The stabilized reference-line (SRL) technique for scaled DRAMsKenji Tsuchida, Yukihito Oowaki, Masako Ohta, Daisaburo Takashima, Shigeyoshi Watanabe, Kazuya Ohuchi, Fujio Masuoka. jssc, 25(1):24-29, February 1990. [doi]

See Also

All Publications

Filter by Year
OR AND NOT 1

Filter by Type
OR AND NOT 1

Filter by Tag
OR AND NOT 1

Filter by Venue
OR AND NOT 1

Filter by Author

[+]
OR AND NOT 1

Filter by Top Terms

[+]
OR AND NOT 1

Researchr

Publications by 'Daisaburo Takashima'

Viewing Publication 1 - 29 from 29

2019

2015

2012

2011

2010

2009

2006

2003

2002

2001

1999

1998

1997

1994

1993

1992

1991

1990

See Also

All Publications

Filter by YearOR AND NOT 1

Filter by TypeOR AND NOT 1

Filter by TagOR AND NOT 1

Filter by VenueOR AND NOT 1

Filter by Author [+]OR AND NOT 1

Filter by Top Terms [+]OR AND NOT 1

Researchr

Publications by 'Daisaburo Takashima'

Viewing Publication 1 - 29 from 29

2019

2015

2012

2011

2010

2009

2006

2003

2002

2001

1999

1998

1997

1994

1993

1992

1991

1990

Filter by Year
OR AND NOT 1

Filter by Type
OR AND NOT 1

Filter by Tag
OR AND NOT 1

Filter by Venue
OR AND NOT 1

Filter by Author

[+]
OR AND NOT 1

Filter by Top Terms

[+]
OR AND NOT 1