Yasuo Itoh - researchr alias

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Viewing Publication 1 - 16 from 16

2014

A Fully Static Topologically-Compressed 21-Transistor Flip-Flop With 75% Power SavingNatsumi Kawai, Shinichi Takayama, Junya Masumi, Naoto Kikuchi, Yasuo Itoh, Kyosuke Ogawa, Akimitsu Ugawa, Hiroaki Suzuki, Yasunori Tanaka. jssc, 49(11):2526-2533, 2014. [doi]

2008

Is the perceived agreeability of a face related to the fractal dimension of the face?Yasuo Itoh, Mayumi Oyama-Higa, Tiejun Miao. SMC 2008: 2960-2965 [doi]

Relationship between fractal dimension and favorability of facial imageryMayumi Oyama-Higa, Tiejun Miao, Yasuo Itoh. ijhis, 5(4):169-178, 2008. [doi]

2007

Does the transition of the interval in perceptional alternation have a chaotic rhythm?Yasuo Itoh, Mayumi Oyama. SMC 2007: 3135-3139 [doi]

2006

Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and BeyondKoichiro Ishibashi, Tetsuya Fujimoto, Takahiro Yamashita, Hiroyuki Okada, Yukio Arima, Yasuyuki Hashimoto, Kohji Sakata, Isao Minematsu, Yasuo Itoh, Haruki Toda, Motoi Ichihashi, Yoshihide Komatsu, Masato Hagiwara, Toshiro Tsukada. ieicet, 89-C(3):250-262, 2006. [doi]

2001

A 76-mm/sup 2/ 8-Mb chain ferroelectric memoryDaisaburo Takashima, Yoshiaki Takeuchi, Tadashi Miyakawa, Yasuo Itoh, Ryu Ogiwara, Masahiro Kamoshida, Katsuhiko Hoya, Sumiko Mano Doumae, Tohru Ozaki, Hiroyuki Kanaya, Koji Yamakawa, Iwao Kunishima, Yukihito Oowaki. jssc, 36(11):1713-1720, 2001. [doi]

2000

A 0.5-/spl mu/m, 3-V 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitorRyu Ogiwara, Sumio Tanaka, Yasuo Itoh, Tadashi Miyakawa, Yoshiaki Takeuchi, Sumiko Mano Doumae, Hiroyuki Takenaka, Iwao Kunishima, Susumu Shuto, Osamu Hidaka, Sumito Ohtsuki, Shin'ichi Tanaka. jssc, 35(4):545-551, 2000. [doi]

1997

1995

A 35 ns cycle time 3.3 V only 32 Mb NAND flash EEPROMYoshihisa Iwata, Ken-ichi Imamiya, Yoshihisa Sugiura, Hiroshi Nakamura, Hideko Oodaira, Masaki Momodomi, Yasuo Itoh, Toshiharu Watanabe, Hitoshi Araki, Kazuhito Narita, Kazunori Masuda, Junichi Miyamoto. jssc, 30(11):1157-1164, November 1995. [doi]

1991

t distributionMasaki Momodomi, Tomoharu Tanaka, Yoshihisa Iwata, Yoshiyuki Tanaka, Hideko Oodaira, Yasuo Itoh, Riichiro Shirota, Kazunori Ohuchi, Fujio Masuoka. jssc, 26(4):492-496, April 1991. [doi]

1990

1989

An experimental 4-Mbit CMOS EEPROM with a NAND-structured cellMasaki Momodomi, Yasuo Itoh, Riichiro Shirota, Yoshihisa Iwata, Ryozo Nakayama, Ryouhei Kirisawa, Tomoharu Tanaka, Seiichi Aritome, Tetsuo Endoh, Kazunori Ohuchi, Fujjo Masuoka. jssc, 24(5):1238-1243, October 1989. [doi]

New nibbled-page architecture for high-density DRAMsKenji Numata, Yukihito Oowaki, Yasuo Itoh, Takahiko Hara, Kenji Tsuchida, Masako Ohta, Shigyoshi Watanabe, Kazunori Ohuchi. jssc, 24(4):900-904, August 1989. [doi]

1983

An adaptive echo canceller using digital signal processor LSI chipsKazunori Ozawa, Takashi Araseki, Yasuo Itoh. icassp 1983: 466-469 [doi]

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