Tsukasa Shirotori - researchr alias

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Viewing Publication 1 - 5 from 5

1993

A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architectureTsuguo Kobayashi, Kazutaka Nogami, Tsukasa Shirotori, Yukihiro Fujimoto. jssc, 28(4):523-527, April 1993. [doi]

1991

A 0.5-W 64-kilobyte snoopy cache memory with pseudo two-port operationTsuguo Kobayashi, Kazutaka Nogami, Tsukasa Shirotori, Yukihiro Fujimoto, Yoshitaka Biwaki, Haruo Nohara, Makiji Kobayashi, Kiyoshi Kobayashi, Kazuhiro Sawada. jssc, 26(11):1586-1592, November 1991. [doi]

1990

A 9-ns HIT-delay 32-kbyte cache macro for high-speed RISCKazutaka Nogami, Takayasu Sakurai, Kazuhiro Sawada, Kenji Sakaue, Yuichi Miyazawa, Shinichi Tanaka, Ypocjo Hiruta, Katsuto Katoh, Toshinari Takayanagi, Tsukasa Shirotori, Yasuo Itoh, Masanori Uchida, Tetsuya Iizuka. jssc, 25(1):100-108, February 1990. [doi]

1989

A 32 kbyte integrated cache memoryKazuhiro Sawada, Takayasu Sakurai, Kazutaka Nogami, Tsukasa Shirotori, Toshinari Takayanagi, Tetsuya Iizuka, Takeo Maeda, Jinichi Matsunaga, Hiromichi Fuji, Kenji Maeguchi, Kiyoshi Kobayashi, Tomoyuki Ando, Yoshiki Hayakashi, Akio Miyoshi, Kazuyuki Sato. jssc, 24(4):881-888, August 1989. [doi]

1988

A 30- mu A data-retention pseudostatic RAM with virtually static RAM modeKazuhiro Sawada, Takayasu Sakurai, Kazutaka Nogami, Katsuhiko Sato, Tsukasa Shirotori, Masakazu Kakuma, Shigeru Morita, Masaaki Kinugawa, Tetsuya Asami, Kazuhito Narita, Jun-Ichi Matsunaga, Akira Higuchi, Mitsuo Isobe, Tetsuya Iizuka. jssc, 23(1):12-19, February 1988. [doi]

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