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Daisaburo Takashima, Susumu Shuto, Iwao Kunishima, Hiroyuki Takenaka, Yukihito Oowaki, Shin'ichi Tanaka. A sub-40-ns chain FRAM architecture with 7-ns cell-plate-line drive. J. Solid-State Circuits, 34(11):1557-1563, 1999. [doi]
Abstract is missing.