Table of Contents

• Session 1 overview: Plenary sessionAnantha Chandrakasan, Hideto Hidaka. 7-9 [doi]
• Flash memory - The great disruptor!Eli Harari. 10-15 [doi]
• The role of semiconductors in the energy landscapeCarmelo Papa. 16-21 [doi]
• Take the expressway to go greenerYoichi Yano. 24-30 [doi]
• Sustainability in silicon and systems developmentDavid Perlmutter. 31-35 [doi]
• Session 2 overview: High-bandwidth DRAM & PRAM: Memory subcommitteeJoo-Sun Choi, Daisaburo Takashima. 36-37 [doi]
• A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch schemeKyomin Sohn, Taesik Na, Indal Song, Yong Shim, Wonil Bae, Sanghee Kang, DongSu Lee, Hangyun Jung, Hanki Jeoung, Ki Won Lee, Junsuk Park, Jongeun Lee, ByungHyun Lee, Inwoo Jun, Juseop Park, Junghwan Park, Hundai Choi, Sanghee Kim, Haeyoung Chung, Young Choi, Dae-Hee Jung, Jang Seok Choi, Byung-Sick Moon, Jung Hwan Choi, Byungchul Kim, Seong-Jin Jang, Joo-Sun Choi, Kyungseok Oh. 38-40 [doi]
• A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architectureKibong Koo, Sunghwa Ok, Yonggu Kang, Seungbong Kim, Choungki Song, Hyeyoung Lee, Hyungsoo Kim, Yongmi Kim, Jeonghun Lee, Seunghan Oak, Yosep Lee, Jungyu Lee, Joongho Lee, Hyungyu Lee, Jaemin Jang, Jongho Jung, Byeongchan Choi, Yongju Kim, Youngdo Hur, Yunsaing Kim, Byong-Tae Chung, Yongtak Kim. 40-41 [doi]
• 2 4Gb DDR3 SDRAM with local-bitline sense amplifier, hybrid LIO sense amplifier and dummy-less array architectureKyu-Nam Lim, Woong-Ju Jang, Hyung-Sik Won, Kang-Yeol Lee, Hyungsoo Kim, Dong-Whee Kim, Mi-Hyun Cho, Seung-Lo Kim, Jong-Ho Kang, Keun-Woo Park, Byung-Tae Jeong. 42-44 [doi]
• A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control schemeYong-Cheol Bae, Joon Young Park, Sang Jae Rhee, Seung Bum Ko, Yonggwon Jeong, Kwang-Sook Noh, Younghoon Son, Jaeyoun Youn, Yonggyu Chu, Hyunyoon Cho, Mijo Kim, Daesik Yim, Hyo-Chang Kim, Sang-Hoon Jung, Hye-In Choi, Sungmin Yim, Jung-Bae Lee, Joo-Sun Choi, Kyungseok Oh. 44-46 [doi]
• A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidthYoungdon Choi, Ickhyun Song, Mu-Hui Park, Hoeju Chung, Sanghoan Chang, Beakhyoung Cho, Jinyoung Kim, Younghoon Oh, Dukmin Kwon, Jung Sunwoo, Junho Shin, Yoohwan Rho, Changsoo Lee, Min Gu Kang, Jaeyun Lee, Yongjin Kwon, Soehee Kim, Jaewhan Kim, Yong-jun Lee, Qi Wang, Sooho Cha, Sujin Ahn, Hideki Horii, Jaewook Lee, KiSeung Kim, Han Sung Joo, KwangJin Lee, Yeong-Taek Lee, Jei-Hwan Yoo, Gitae Jeong. 46-48 [doi]
• A 283.2μW 800Mb/s/pin DLL-based data self-aligner for Through-Silicon Via (TSV) interfaceHyun-Woo Lee, Soo-Bin Lim, Junyoung Song, Jabeom Koo, Dae-Han Kwon, Jong-Ho Kang, Yunsaing Kim, Young-Jung Choi, Kunwoo Park, Byong-Tae Chung, Chulwoo Kim. 48-50 [doi]
• An 8Gb/s/pin 4pJ/b/pin Single-T-Line dual (base+RF) band simultaneous bidirectional mobile memory I/O interface with inter-channel interference suppressionYanghyo Kim, Gyungsu Byun, Adrian Tang 0002, Chewnpu Jou, Hsieh-Hung Hsieh, Glenn Reinman, Jason Cong, Mau-Chung Frank Chang. 50-52 [doi]
• A 7Gb/s/link non-contact memory module for multi-drop bus system using energy-equipartitioned coupled transmission lineWon-Joo Yun, Shinya Nakano, Wataru Mizuhara, Atsutake Kosuge, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda. 52-54 [doi]
• Session 3 overview: Processors: High performance digital subcommitteeJoshua Friedrich, Jinuk Luke Shin. 54-55 [doi]
• A 22nm IA multi-CPU and GPU System-on-ChipSatish Damaraju, George Varghese, Sanjeev Jahagirdar, Tanveer Khondker, Robert Milstrey, Sanjib Sarkar, Scott Siers, Israel Stolero, Arun Subbiah. 56-57 [doi]
• A 32-core RISC microprocessor with network accelerators, power management and testability featuresBrian Miller, Derek Brasili, Tim Kiszely, Rob Kuhn, Rahul Mehrotra, Manan Salvi, Mandar Kulkarni, Anand Varadharajan, Shi-Huang Yin, William Lin, Adam Hughes, Bill Stysiack, Vasu Kandadi, Ilan Pragaspathi, Dan Hartman, David Carlson, Vishnu Yalala, Thucydides Xanthopoulos, Scott Meninger, Ethan Crain, Mark Spaeth, Akin Aina, Suresh Balasubramanian, Joe Vulih, Pragati Tiwary, David Lin, Richard Kessler, Bruce Fishbein, Anil Jain. 58-60 [doi]
• The next-generation 64b SPARC core in a T4 SoC processorJinuk Luke Shin, Heechoul Park, Hongping Li, Alan Smith, Youngmoon Choi, Harikaran Sathianathan, Sudesna Dash, Sebastian Turullols, Song Kim, Robert Masleid, Georgios Konstadinidis, Robert T. Golla, Mary Jo Doherty, Greg Grohoski, Curtis McAllister. 60-62 [doi]
• 32nm x86 OS-compliant PC on-chip with dual-core Atom® processor and RF WiFi transceiverHasnain Lakdawala, Mark Schaecher, Chang-Tsung Fu, Rahul Limaye, Jon Duster, Yulin Tan, Ajay Balankutty, Erkan Alpman, Chun C. Lee, Satoshi Suzuki, Brent R. Carlton, Hyung Seok Kim, Marian Verhelst, Stefano Pellerano, Tong Kim, Durgesh Srivastava, Satish Venkatesan, Hyung-Jin Lee, Peter Vandervoorn, Jad Rizk, Chia-Hong Jan, Krishnamurthy Soumyanath, Sunder Ramamurthy. 62-64 [doi]
• An 800MHz 320mW 16-core processor with message-passing and shared-memory inter-core communication mechanismsZhiyi Yu, Kaidi You, Ruijin Xiao, Heng Quan, Peng Ou, Yan Ying, HaoFan Yang, Ming-e Jing, Xiaoyang Zeng. 64-66 [doi]
• A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOSShailendra Jain, Surhud Khare, Satish Yada, V. Ambili, Praveen Salihundam, Shiva Ramani, Sriram Muthukumar, M. Srinivasan, Arun Kumar, Shasi Kumar, Rajaraman Ramanarayanan, Vasantha Erraguntla, Jason Howard, Sriram R. Vangal, Saurabh Dighe, Gregory Ruhl, Paolo A. Aseron, Howard Wilson, Nitin Borkar, Vivek De, Shekhar Borkar. 66-68 [doi]
• Resonant clock design for a power-efficient high-volume x86-64 microprocessorVisvesh S. Sathe, Srikanth Arekapudi, Charles Ouyang, Marios C. Papaefthymiou, Alexander T. Ishii, Samuel Naffziger. 68-70 [doi]
• A reconfigurable distributed all-digital clock generator core with SSC and skew correction in 22nm high-k tri-gate LP CMOSY. William Li, Carlos Ornelas, Hyung Seok Kim, Hasnain Lakdawala, Ashoke Ravi, Krishnamurthy Soumyanath. 70-72 [doi]
• Session 4 overview: RF techniques: RF subcommitteeMasoud Zargari, Songcheol Hong. 72-73 [doi]
• A blocker-tolerant wideband noise-cancelling receiver with a 2dB noise figureDavid Murphy, Amr Hafez, Ahmad Mirzaei, Mohyee Mikhemar, Hooman Darabi, Mau-Chung Frank Chang, Asad A. Abidi. 74-76 [doi]
• 8-Path tunable RF notch filters for blocker suppressionAmir Ghaffari, Eric A. M. Klumperink, Bram Nauta. 76-78 [doi]
• A wideband IM3 cancellation technique for CMOS attenuatorsWei Cheng, Mark S. Oude Alink, Anne-Johan Annema, Gerard Wienk, Bram Nauta. 78-80 [doi]
• A 1-to-2.5GHz phased-array IC based on gm-RC all-pass time-delay cellsSeyed Kasra Garakoui, Eric A. M. Klumperink, Bram Nauta, Frank E. van Vliet. 80-82 [doi]
• A fully integrated dual-mode CMOS power amplifier for WCDMA applicationsBonhoon Koo, Taehwan Joo, Yoosam Na, Songcheol Hong. 82-84 [doi]
• A 28.3mW PA-closed loop for linearity and efficiency improvement integrated in a +27.1dBm WCDMA CMOS power amplifierShouhei Kousai, Kohei Onizuka, Takashi Yamaguchi, Yasuhiko Kuriyama, Masami Nagaoka. 84-86 [doi]
• A fully integrated triple-band CMOS power amplifier for WCDMA mobile handsetsKouichi Kanda, Yoichi Kawano, Takao Sasaki, Noriaki Shirai, Tetsuro Tamura, Shigeaki Kawai, Masahiro Kudo, Tomotoshi Murakami, Hiroyuki Nakamoto, Nobumasa Hasegawa, Hideki Kano, Nobuhiro Shimazui, Akiko Mineyama, Kazuaki Oishi, Masashi Shima, Naoyoshi Tamura, Toshihide Suzuki, Toshihiko Mori, Kimitoshi Niratsuka, Shinji Yamaura. 86-88 [doi]
• A 45nm SOI CMOS Class-D mm-Wave PA with >10Vpp differential swingIoannis Sarkas, Andreea Balteanu, Eric Dacquay, Alexander Tomkins, Sorin P. Voinigescu. 88-90 [doi]
• Session 5 overview: Audio and power converters: Analog subcommitteeWing-Hung Ki, Jed Hurwitz. 90-91 [doi]
• An 8Ω 2.5W 1%-THD 104dB(A)-dynamic-range Class-D audio amplifier with an ultra-low EMI system and current sensing for speaker protectionAngelo Nagari, Emmanuel Allier, Francois Amiard, Vincent Binet, Christian Fraisse. 92-94 [doi]
• A 1.5W 10V-output Class-D amplifier using a boosted supply from a single 3.3V input in standard 1.8V/3.3V 0.18μm CMOSBert Serneels, Eldert Geukens, Bram De Muer, Tim Piessens. 94-96 [doi]
• A 0.028% THD+N, 91% power-efficiency, 3-level PWM Class-D amplifier with a true differential front-endSunwoo Kwon, Injeong Kim, Shinyoung Yi, Sangheyub Kang, Sangheon Lee, Taeho Hwang, Byoungkwon Moon, Yunyoung Choi, Hosung Sung, Jinseok Koh. 96-98 [doi]
• A 41-phase switched-capacitor power converter with 3.8mV output ripple and 81% efficiency in baseline 90nm CMOSGerard Villar Pique. 98-100 [doi]
• A high-voltage CMOS IC and embedded system for distributed photovoltaic energy optimization with over 99% effective conversion efficiency and insertion loss below 0.1%Jason Stauth, Michael D. Seeman, Kapil Kesarwani. 100-102 [doi]
• A maximum power-point tracker without digital signal processing in 0.35μm CMOS for automotive applicationsReinhard Enne, Miodrag Nikolic, Horst Zimmermann. 102-104 [doi]
• A 40mV transformer-reuse self-startup boost converter with MPPT control for thermoelectric energy harvestingJong-Pil Im, Se-Won Wang, Kang-Ho Lee, Young-Jin Woo, Young-sub Yuk, Tae-Hwang Kong, Sung-Wan Hong, Seung-Tak Ryu, Gyu-Hyeong Cho. 104-106 [doi]
• A 330nA energy-harvesting charger with battery management for solar and thermoelectric energy harvestingKarthik Kadirvel, Yogesh K. Ramadass, Umar Lyles, John Carpenter, Vadim Ivanov, Vince McNeil, Anantha Chandrakasan, Brian Lum-Shue-Chan. 106-108 [doi]
• Session 6 overview: Medical, displays and imagers: Imagers, MEMS, medical and displays subcommitteeYusuke Oike, Maysam Ghovanloo. 108-109 [doi]
• A sampling-based 128×128 direct photon-counting X-ray image sensor with 3 energy bins and spatial resolution of 60μm/pixelHyunsik Kim, Sang-Wook Han, Junhyeok Yang, Sung-Il Kim, Young Kim, Sangwook Kim, Dae-Kun Yoon, Jun Su Lee, Jae-Chul Park, Younghun Sung, Seong-Deok Lee, Seung-Tak Ryu, Gyu-Hyeong Cho. 110-112 [doi]
• A 1.36μW adaptive CMOS image sensor with reconfigurable modes of operation from available energy/illumination for distributed wireless sensor networkJaehyuk Choi, Seokjun Park, Jihyun Cho, Euisik Yoon. 112-114 [doi]
• A 0.5V 4.95μW 11.8fps PWM CMOS imager with 82dB dynamic range and 0.055% fixed-pattern noiseMeng-Ting Chung, Chih-Cheng Hsieh. 114-116 [doi]
• A capacitive touch controller robust to display noise for ultrathin touch screen displaysKi-Duk Kim, San-Ho Byun, Yoon Kyung Choi, Jong-Hak Baek, Hwa-Hyun Cho, Jong Kang Park, Hae-Yong Ahn, Chang-ju Lee, Min-Soo Cho, Joo-Hyeon Lee, Sang-Woo Kim, Hyung-Dal Kwon, Yong-Yeob Choi, Hosuk Na, Junchul Park, Yeon-Joong Shin, Kyungsuk Jang, Gyoocheol Hwang, Myunghee Lee. 116-117 [doi]
• A 160μA biopotential acquisition ASIC with fully integrated IA and motion-artifact suppressionNick Van Helleputte, Sunyoung Kim, Hyejung Kim, Jong Pal Kim, Chris Van Hoof, Refet Firat Yazicioglu. 118-120 [doi]
• CMOS capacitive biosensor with enhanced sensitivity for label-free DNA detectionKang-Ho Lee, Sukhwan Choi, Jeong Oen Lee, Jun-Bo Yoon, Gyu-Hyeong Cho. 120-122 [doi]
• A 100Mphoton/s time-resolved mini-silicon photomultiplier with on-chip fluorescence lifetime estimation in 0.13μm CMOS imaging technologyDavid Tyndall, Bruce Rae, David Day-Uei Li, Justin A. Richardson, Jochen Arlt, Robert K. Henderson. 122-124 [doi]
• A wireless magnetoresistive sensing system for an intra-oral tongue-computer interfaceHangue Park, Benoit Gosselin, Mehdi Kiani, Hyung-Min Lee, Jeonghee Kim, Xueliang Huo, Maysam Ghovanloo. 124-126 [doi]
• A CMOS 10kpixel baseline-free magnetic bead detector with column-parallel readout for miniaturized immunoassaysSimone Gambini, Karl Skucha, Paul Peng Liu, Jungkyu Kim, Reut Krigel, Richard Mathies, Bernhard E. Boser. 126-128 [doi]
• Session 7 overview: Multi-Gb/s receiver and parallel I/O techniques: Wireline subcommitteeRobert Payne, Tatsuya Saito. 128-129 [doi]
• An 18.6Gb/s double-sampling receiver in 65nm CMOS for ultra-low-power optical communicationMeisam Honarvar Nazari, Azita Emami-Neyestanak. 130-131 [doi]
• A 0.4mW/Gb/s 16Gb/s near-ground receiver front-end with replica transconductance termination calibrationKambiz Kaviani, Amir Amirkhany, Charlie Huang, Phuong Le, Chris J. Madden, Keisuke Saito, Koji Sano, Vinod Murugan, Wendemagegnehu T. Beyene, Ken Chang, Chuck Yuan. 132-134 [doi]
• A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOSAnkur Agrawal, John F. Bulzacchelli, Timothy O. Dickson, Yong Liu, José A. Tierno, Daniel J. Friedman. 134-136 [doi]
• An 8GB/s quad-skew-cancelling parallel transceiver in 90nm CMOS for high-speed DRAM interfaceYoung-Sik Kim, Seon-Kyoo Lee, Seung-Jun Bae, Young-Soo Sohn, Jung-Bae Lee, Joo-Sun Choi, Hong June Park, Jae-Yoon Sim. 136-138 [doi]
• A 4.1pJ/b 16Gb/s coded differential bidirectional parallel electrical linkAmir Amirkhany, Kambiz Kaviani, Ali-Azam Abbasfar, H. Md. Shuaeb Fazeel, Wendemagegnehu T. Beyene, Chikara Hoshino, Chris J. Madden, Ken Chang, Chuck Yuan. 138-140 [doi]
• A 5Gb/s single-ended parallel receiver with adaptive FEXT cancellationSeon-Kyoo Lee, Hyunsoo Ha, Hong June Park, Jae-Yoon Sim. 140-142 [doi]
• A compact low-power 3D I/O in 45nm CMOSYong Liu, Wing Luk, Daniel J. Friedman. 142-144 [doi]
• Session 8 overview: Delta-sigma converters: Data converters subcommitteeBrian Brandt, Gerhard Mitteregger. 144-145 [doi]
• An LC bandpass ΔΣ ADC with 70dB SNDR over 20MHz bandwidth using CMOS DACsJeffrey Harrison, Michal Nesselroth, Robert Mamuad, Arya Behzad, Andrew Adams, Steve Avery. 146-148 [doi]
• A 12mW low-power continuous-time bandpass ΔΣ modulator with 58dB SNDR and 24MHz bandwidth at 200MHz IFHyungil Chae, Jaehun Jeong, Gabriele Manganaro, Michael Flynn. 148-150 [doi]
• A DC-to-1GHz tunable RF ΔΣ ADC achieving DR = 74dB and BW = 150MHz at f0 = 450MHz using 550mWHajime Shibata, Richard Schreier, Wenhua Yang, Ali Shaikh, Donald Paterson, Trevor C. Caldwell, David Alldred, Ping Wing Lai. 150-152 [doi]
• A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizerKarthikeyan Reddy, Sachin Rao, Rajesh Inti, Brian Young, Amr Elshazly, Mrunmay Talegaonkar, Pavan Kumar Hanumolu. 152-154 [doi]
• A 72dB-DR ΔΣ CT modulator using digitally estimated auxiliary DAC linearization achieving 88fJ/conv in a 25MHz BWPascal Witte, John G. Kauffman, Joachim Becker, Yiannos Manoli, Maurits Ortmanns. 154-156 [doi]
• A 15mW 3.6GS/s CT-ΔΣ ADC with 36MHz bandwidth and 83dB DR in 90nm CMOSPradeep Shettigar, Shanthi Pavan. 156-158 [doi]
• rd-order continuous-time delta-sigma modulator clocked at 6GHz in 45nm CMOSVenkatesh Srinivasan, Victoria Wang, Patrick Satarzadeh, Baher Haroun, Marco Corsi. 158-160 [doi]
• Session 9 overview: Wireless transceiver techniques: Wireless subcommitteeSven Mattisson, Shouhei Kousai. 160-161 [doi]
• A 40MHz-to-1GHz fully integrated multistandard silicon tuner in 80nm CMOSJody Greenberg, Fernando De Bernardinis, Carlo Tinella, Antonio Milani, Johnny Pan, Paola Uggetti, Marco Sosio, Shaoan Dai, Sam Tang, Giovanni Cesura, Gabriele Gandolfi, Vittorio Colonna, Rinaldo Castello. 162-164 [doi]
• A multiband multimode transmitter without driver amplifierOmid Oliaei, Mark Kirschenmann, David Newman, Kurt Hausmann, Haolu Xie, Patrick Rakers, Mahib Rahman, Michael Gomez, Chuanzhao Yu, Benjamin Gilsdorf, Kurt Sakamoto. 164-166 [doi]
• 2 in 65nm CMOSShadi Youssef, Ronan A. R. van der Zee, Bram Nauta. 166-168 [doi]
• A 20dBm 2.4GHz digital outphasing transmitter for WLAN application in 32nm CMOSPaolo Madoglio, Ashoke Ravi, Hongtao Xu, Kailash Chandrashekar, Marian Verhelst, Stefano Pellerano, Luis Cuellar, Mariano Aguirre, Masoud Sajadieh, Ofir B. Degani, Hasnain Lakdawala, Yorgos Palaskas. 168-170 [doi]
• A 60GHz outphasing transmitter in 40nm CMOS with 15.6dBm output powerDixian Zhao, Shailesh Kulkarni, Patrick Reynaert. 170-172 [doi]
• A 4-in-1 (WiFi/BT/FM/GPS) connectivity SoC with enhanced co-existence performance in 65nm CMOSYuan-Hung Chung, Min Chen, Wei-Kai Hong, Jie-Wei Lai, Sheng-Jau Wong, Chien-Wei Kuan, Hong-Lin Chu, Chihun Lee, Chih-Fan Liao, Hsuan-Yu Liu, Hong-Kai Hsu, Li-chun Ko, Kuo-Hao Chen, Chao-Hsin Lu, Tsung-Ming Chen, YuLi Hsueh, Chunwei Chang, Yi-Hsien Cho, Chih-Hsien Shen, Yuan Sun, Eng-Chuan Low, Xudong Jiang, Deyong Hu, Weimin Shu, Jhy-Rong Chen, Jui-Lin Hsu, Chia-Jui Hsu, Jing-Hong Conan Zhan, Osama Shana'a, Guang-Kaai Dehng, George Chien. 172-174 [doi]
• A 1.5-to-5.0GHz input-matched +2dBm P1dB all-passive switched-capacitor beamforming receiver front-end in 65nm CMOSMichiel C. M. Soer, Eric A. M. Klumperink, Bram Nauta, Frank E. van Vliet. 174-176 [doi]
• Session 10 overview: High-performance digital: High performance digital subcommitteeLew Chua-Eoan, Se-Hyun Yang. 176-177 [doi]
• A 280mV-to-1.1V 256b reconfigurable SIMD vector permutation engine with 2-dimensional shuffle in 22nm CMOSSteven Hsu, Amit Agarwal, Mark Anders, Sanu Mathew, Himanshu Kaul, Farhana Sheikh, Ram Krishnamurthy. 178-180 [doi]
• A source-synchronous 90Gb/s capacitively driven serial on-chip link over 6mm in 65nm CMOSDennis Walter, Sebastian Höppner, Holger Eisenreich, Georg Ellguth, Stephan Henker, Stefan Hänzsche, René Schüffny, Markus Winter 0002, Gerhard Fettweis. 180-182 [doi]
• A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOSHimanshu Kaul, Mark Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Farhana Sheikh, Ram Krishnamurthy, Shekhar Borkar. 182-184 [doi]
• A 2.05GVertices/s 151mW lighting accelerator for 3D graphics vertex and pixel shading in 32nm CMOSFarhana Sheikh, Sanu Mathew, Mark Anders, Himanshu Kaul, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar. 184-186 [doi]
• A 3D system prototype of an eDRAM cache stacked over processor-like logic using through-silicon viasMatt Wordeman, Joel Silberman, Gary Maier, Michael Scheuermann. 186-187 [doi]
• 3D-MAPS: 3D Massively parallel processor with stacked memoryDae-Hyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim. 188-190 [doi]
• Centip3De: A 3930DMIPS/W configurable near-threshold 3D stacked system with 64 ARM Cortex-M3 coresDavid Fick, Ronald G. Dreslinski, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman Liu, Michael Wieckowski, Gregory K. Chen, Trevor N. Mudge, Dennis Sylvester, David Blaauw. 190-192 [doi]
• K computer: 8.162 PetaFLOPS massively parallel scalar supercomputer built with over 548k coresHiroyuki Miyazaki, Yoshihiro Kusano, Hiroshi Okano, Tatsumi Nakada, Ken Seki, Toshiyuki Shimizu, Naoki Shinjo, Fumiyoshi Shoji, Atsuya Uno, Motoyoshi Kurokawa. 192-194 [doi]
• Session 11 overview: Sensors and MEMS: Imagers, MEMS, medical and displays subcommitteeChristoph Hagleitner, Maurits Ortmanns. 194-195 [doi]
• A ΔΣ interface for MEMS accelerometers using electrostatic spring-constant modulation for cancellation of bondwire capacitance driftPedram Lajevardi, Vladimir P. Petkov, Boris Murmann. 196-198 [doi]
• A capacitance-to-digital converter for displacement sensing with 17b resolution and 20μs conversion timeSha Xia, Kofi A. A. Makinwa, Stoyan Nihtianov. 198-200 [doi]
• A 50μW biasing feedback loop with 6ms settling time for a MEMS microphone with digital outputJeroen van den Boom. 200-202 [doi]
• ASIC for a resonant wireless pressure-sensing system for harsh environments achieving ±2% error between -40 and 150°C using Q-based temperature compensationMarko Rocznik, Fabian Henrici, Remigius Has. 202-204 [doi]
• A ±0.4°C (3σ) -70 to 200°C time-domain temperature sensor based on heat diffusion in Si and SiO2Caspar P. L. van Vroonhoven, Dan d'Aquino, Kofi A. A. Makinwa. 204-206 [doi]
• A temperature-to-digital converter for a MEMS-based programmable oscillator with better than ±0.5ppm frequency stabilityMichael H. Perrott, Jim Salvia, Fred S. Lee, Aaron Partridge, Shouvik Mukherjee, Carl Arft, Jin Tae Kim, Niveditha Arumugam, Pavan Gupta, Sassan Tabatabaei, Sudhakar Pamarti, Haechang Lee, Fari Assaderaghi. 206-208 [doi]
• A CMOS temperature sensor with a voltage-calibrated inaccuracy of ±0.15°C (3σ) from -55 to 125°CKamran Souri, Youngcheol Chae, Kofi A. A. Makinwa. 208-210 [doi]
• Ratiometric BJT-based thermal sensor in 32nm and 22nm technologiesJoseph Shor, Kosta Luria, Dror Zilberman. 210-212 [doi]
• Session 12 overview: Multimedia and communications SoCs: Energy-efficient digital subcommitteeByeong-Gyu Nam, Shannon Morton. 212-213 [doi]
• A 32nm high-k metal gate application processor with GHz multi-core CPUSe-Hyun Yang, Seogjun Lee, Jae Young Lee, Jeonglae Cho, Hoi-Jin Lee, Dongsik Cho, Junghun Heo, Sunghoon Cho, Youngmin Shin, Sunghee Yun, Euiseok Kim, Ukrae Cho, Edward Pyo, Man Hyuk Park, Jae Cheol Son, Chinhyun Kim, Jeongnam Youn, Youngki Chung, Sungho Park, Seung Ho Hwang. 214-216 [doi]
• 2 65nm CMOS flexible MIMO detection-decoding engine achieving 4G wireless data ratesMarkus Winter 0002, Steffen Kunze, Esther P. Adeva, Björn Mennenga, Emil Matús, Gerhard Fettweis, Holger Eisenreich, Georg Ellguth, Sebastian Höppner, Stefan Scholze, René Schüffny, Tomoyoshi Kobori. 216-218 [doi]
• A full 4-channel 6.3Gb/s 60GHz direct-conversion transceiver with low-power analog and digital baseband circuitryKenichi Okada, Keitarou Kondou, Masaya Miyahara, Masashi Shinagawa, Hiroki Asada, Ryo Minami, Tatsuya Yamaguchi, Ahmed Musa, Yuuki Tsukui, Yasuo Asakura, Shinya Tamonoki, Hiroyuki Yamagishi, Yasufumi Hino, Takahiro Sato, Hironori Sakaguchi, Naoki Shimasaki, Toshihiko Ito, Yasuaki Takeuchi, Ning Li, Qinghong Bu, Rui Murakami, Keigo Bunsen, Kota Matsushita, Makoto Noda, Akira Matsuzawa. 218-220 [doi]
• A 320mW 342GOPS real-time moving object recognition processor for HD 720p video streamsJinwook Oh, Gyeonghoon Kim, Junyoung Park, Injoon Hong, Seungjin Lee, Hoi-Jun Yoo. 220-222 [doi]
• A 464GOPS 620GOPS/W heterogeneous multi-core SoC for image-recognition applicationsYasuki Tanabe, Masato Sumiyoshi, Manabu Nishiyama, Itaru Yamazaki, Shinsuke Fujii, Katsuyuki Kimura, Takuma Aoyama, Moriyasu Banno, Hiroo Hayashi, Takashi Miyamori. 222-223 [doi]
• A 2Gpixel/s H.264/AVC HP/MVC video decoder chip for Super Hi-Vision and 3DTV/FTV applicationsDajiang Zhou, Jinjia Zhou, Jiayi Zhu, Peilin Liu, Satoshi Goto. 224-226 [doi]
• A true multistandard, programmable, low-power, full HD video-codec engine for smartphone SoCMahesh Mehendale, Subrangshu Das, Mohit Sharma, Mihir Mody, Ratna Reddy, Joseph Meehan, Hideo Tamama, Brian Carlson, Mike Polley. 226-228 [doi]
• Session 13 overview: High-performance embedded SRAM: Memory subcommitteeLeland Chang, Michael Clinton. 228-229 [doi]
• A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitryEric Karl, Yih Wang, Yong-Gee Ng, Zheng Guo, Fatih Hamzaoglu, Uddalak Bhattacharya, Kevin Zhang, Kaizad Mistry, Mark Bohr. 230-232 [doi]
• A 6T SRAM with a carrier-injection scheme to pinpoint and repair fails that achieves 57% faster read and 31% lower read energyKousuke Miyaji, Toshikazu Suzuki, Shinji Miyano, Ken Takeuchi. 232-234 [doi]
• Capacitive-coupling wordline boosting with self-induced VCC collapse for write VMIN reduction in 22-nm 8T SRAMJaydeep Kulkarni, Bibiche M. Geuskens, Tanay Karnik, Muhammad M. Khellah, James Tschanz, Vivek De. 234-236 [doi]
• A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbsYuichiro Ishii, Yasumasa Tsukamoto, Koji Nii, Hidehiro Fujiwara, Makoto Yabuuchi, Koji Tanaka, Shinji Tanaka, Yasuhisa Shimazaki. 236-238 [doi]
• Session 14 overview: Digital clocking and PLLs: High-performance digital subcommitteeAnthony Hill, Hiroo Hayashi. 238-239 [doi]
• 2 2.5mW bang-bang digital PLL using PRNG for low-power SoC applicationsJong-Phil Hong, Sung Jin Kim, Jenlung Liu, Nan Xing, Tae-Kwang Jang, Jaejin Park, Jihyun F. Kim, Taeik Kim, Hojin Park. 240-242 [doi]
• A 1.5GHz 890μW digital MDLL with 400fsrms integrated jitter, -55.6dBc reference spur and 20fs/mV supply-noise sensitivity using 1b TDCAmr Elshazly, Rajesh Inti, Brian Young, Pavan Kumar Hanumolu. 242-244 [doi]
• 2 fast-locking all-digital DLL in 90nm CMOSMin-Han Hsieh, Liang-Hsin Chen, Shen-Iuan Liu, Charlie Chung-Ping Chen. 244-246 [doi]
• A TDC-less ADPLL with 200-to-3200MHz range and 3mW power dissipation for mobile SoC clocking in 22nm CMOSNathaniel J. August, Hyung-Jin Lee, Martin Vandepas, Rachael Parker. 246-248 [doi]
• A digitally stabilized type-III PLL using ring VCO with 1.01psrms integrated jitter in 65nm CMOSAkihide Sai, Yuka Kobayashi, Shigehito Saigusa, Osamu Watanabe, Tetsuro Itakura. 248-250 [doi]
• Session 15 overview: Mm-Wave and THz techniques: RF subcommitteeEhsan Afshari, Yorgos Palaskas. 250-251 [doi]
• A 1kpixel CMOS camera chip for 25fps real-time terahertz imaging applicationsHani Sherry, Janus Grzyb, Yan Zhao, Richard Al Hadi, Andreia Cathelin, Andreas Kaiser, Ullrich R. Pfeiffer. 252-254 [doi]
• 280GHz and 860GHz image sensors using Schottky-barrier diodes in 0.13μm digital CMOSRuonan Han, Yaming Zhang, Youngwan Kim, Dae-Yeon Kim, Hisashi Shichijo, Ehsan Afshari, K. O. Kenneth. 254-256 [doi]
• A 0.28THz 4×4 power-generation and beam-steering arrayKaushik Sengupta, Ali Hajimiri. 256-258 [doi]
• A 283-to-296GHz VCO with 0.76mW peak output power in 65nm CMOSYahya M. Tousi, Omeed Momeni, Ehsan Afshari. 258-260 [doi]
• A 1V 19.3dBm 79GHz power amplifier in 65nm CMOSKun-Yin Wang, Tao-Yao Chang, Chorng-Kuang Wang. 260-262 [doi]
• A 9% power efficiency 121-to-137GHz phase-controlled push-push frequency quadrupler in 0.13μm SiGe BiCMOSYong Wang, Wang Ling Goh, Yong-Zhong Xiong. 262-264 [doi]
• A 144GHz 0.76cm-resolution sub-carrier SAR phase radar for 3D imaging in 65nm CMOSAdrian Tang 0002, Gabriel Virbila, David Murphy, Frank Hsiao, Yen-Hsiang Wang, Qun Jane Gu, Zhiwei Xu, Y. Wu, M. Zhu, Mau-Chung Frank Chang. 264-266 [doi]
• A 2Gb/s-throughput CMOS transceiver chipset with in-package antenna for 60GHz short-range wireless communicationToshiya Mitomo, Yukako Tsutsumi, Hiroaki Hoshino, Masahiro Hosoya, Tong Wang, Yuta Tsubouchi, Ryoichi Tachibana, Akihide Sai, Yuka Kobayashi, Daisuke Kurose, Tomohiko Ito, Koichiro Ban, Tomoya Tandai, Takeshi Tomizawa. 266-268 [doi]
• A low-power 57-to-66GHz transceiver in 40nm LP CMOS with -17dB EVM at 7Gb/sVojkan Vidojkovic, Giovanni Mangraviti, Khaled Khalaf, Viki Szortyka, Kristof Vaesen, Wim Van Thillo, Bertrand Parvais, Mike Libois, Steven Thijs, John R. Long, Charlotte Soens, Piet Wambacq. 268-270 [doi]
• A 4-path 42.8-to-49.5GHz LO generation with automatic phase tuning for 60GHz phased-array receiversLiang Wu, Alvin Li, Howard C. Luong. 270-272 [doi]
• Session 16 overview: Switching power control techniques: Analog subcommitteeBaher Haroun, Gyu-Hyeong Cho. 272-273 [doi]
• 2 in 65nm CMOSChien-Wei Kuan, Hung-Chih Lin. 274-276 [doi]
• A high-stability emulated absolute current hysteretic control single-inductor 5-output switching DC-DC converter with energy sharing and balancingSe-Won Wang, Gyu-Ha Cho, Gyu-Hyeong Cho. 276-278 [doi]
• Off-the-line primary-side regulation LED lamp driver with single-stage PFC and TRIAC dimming using LED forward-voltage and duty-variation tracking controlJong Tae Hwang, Moon Sang Jung, Dae Ho Kim, Jun Hong Lee, Minho Jung, Jong-Shin Ha. 278-280 [doi]
• A 0.18μm CMOS 91%-efficiency 0.1-to-2A scalable buck-boost DC-DC converter for LED driversPiero Malcovati, Massimiliano Belloni, Fabio Gozzini, Cristiano Bazzani, Andrea Baschirotto. 280-282 [doi]
• A 92%-efficiency wide-input-voltage-range switched-capacitor DC-DC converterVincent Ng, Seth Sanders. 282-284 [doi]
• An optimized driver for SiC JFET-based switches delivering more than 99% efficiencyKarl Norling, Christian Lindholm, Dieter Draxelmayr. 284-286 [doi]
• An adaptive reconfigurable active voltage doubler/rectifier for extended-range inductive power transmissionHyung-Min Lee, Maysam Ghovanloo. 286-288 [doi]
• Voltage-boosting wireless power delivery system with fast load tracker by ΔΣ-modulated sub-harmonic resonant switchingRyota Shinoda, Kazutoshi Tomita, Yuya Hasegawa, Hiroki Ishikuro. 288-290 [doi]
• Session 17 overview: Diagnostic and therapeutic technologies for health: Technology directions subcommitteeAlison Burdett, Fu-Lung Hsueh. 290-291 [doi]
• An 8-channel scalable EEG acquisition SoC with fully integrated patient-specific seizure classification and recording processorJerald Yoo, Long Yan, Dina El-Damak, Muhammad Bin Altaf, Ali H. Shoeb, Hoi-Jun Yoo, Anantha Chandrakasan. 292-294 [doi]
• A 259.6μW nonlinear HRV-EEG chaos processor with body channel communication interface for mental health monitoringTaehwan Roh, Sunjoo Hong, Hyunwoo Cho, Hoi-Jun Yoo. 294-296 [doi]
• A sub-10nA DC-balanced adaptive stimulator IC with multimodal sensor for compact electro-acupuncture systemKiseok Song, Hyungwoo Lee, Sunjoo Hong, Hyunwoo Cho, Hoi-Jun Yoo. 296-298 [doi]
• A batteryless 19μW MICS/ISM-band energy harvesting body area sensor node SoCFan Zhang, Yanqing Zhang, Jason Silver, Yousef Shakhsheer, Manohar Nagaraju, Alicia Klinefelter, Jagdish Nayayan Pandey, James Boley, Eric J. Carlson, Aatmesh Shrivastava, Brian P. Otis, Benton H. Calhoun. 298-300 [doi]
• A 1V 5mA multimode IEEE 802.15.6/bluetooth low-energy WBAN transceiver for biotelemetry applicationsAlan Wong, Mark Dawkins, Gabriele Devita, Nick Kasparidis, Andreas G. Katsiamis, Oliver King, Franco Lauria, Johannes Schiff, Alison Burdett. 300-302 [doi]
• A mm-sized wirelessly powered and remotely controlled locomotive implantable deviceAnatoly Yakovlev, Daniel Pivonka, Teresa H. Meng, Ada S. Y. Poon. 302-304 [doi]
• A CMOS impedance cytometer for 3D flowing single-cell real-time analysis with ΔΣ error correctionKang-Ho Lee, Jeonghun Nam, Sukhwan Choi, Hyunjung Lim, Sehyun Shin, Gyu-Hyeong Cho. 304-306 [doi]
• Session 18 overview: Innovative circuits in emerging technologies: Technology directions subcommitteeMasaitsu Nakajima, Shekhar Borkar. 306-307 [doi]
• Insole pedometer with piezoelectric energy harvester and 2V organic digital and analog circuitsKoichi Ishida, Tsung-Ching Huang, Kentaro Honda, Yasuhiro Shinozuka, Hiroshi Fuketa, Tomoyuki Yokota, Ute Zschieschang, Hagen Klauk, Gregory Tortissier, Tsuyoshi Sekitani, Makoto Takamiya, Hiroshi Toshiyoshi, Takao Someya, Takayasu Sakurai. 308-310 [doi]
• 1D and 2D analog 1.5kHz air-stable organic capacitive touch sensors on plastic foilHagen Marien, Michiel Steyaert, Erik van Veenendaal, Paul Heremans. 310-312 [doi]
• Bidirectional communication in an HF hybrid organic/solution-processed metal-oxide RFID tagKris Myny, Maarten Rockele, Adrian Chasin, Duy-Vu Pham, Jürgen Steiger, Silviu Botnaras, Dennis Weber, Bernhard Herold, Jürgen Ficker, Bas van der Putten, Gerwin H. Gelinck, Jan Genoe, Wim Dehaene, Paul Heremans. 312-314 [doi]
• A 6b 10MS/s current-steering DAC manufactured with amorphous Gallium-Indium-Zinc-Oxide TFTs achieving SFDR > 30dB up to 300kHzDaniele Raiteri, Fabrizio Torricelli, Kris Myny, Manoj Nag, Bas van der Putten, Edsger Smits, Soeren Steudel, Karin Tempelaars, Ashutosh Tripathi, Gerwin H. Gelinck, Arthur H. M. van Roermund, Eugenio Cantatore. 314-316 [doi]
• A low-overhead self-healing embedded system for ensuring high yield and long-term sustainability of 60GHz 4Gb/s radio-on-a-chipAdrian Tang 0002, Frank Hsiao, David Murphy, I.-Ning Ku, Jenny Yi-Chun Liu, Sandeep D'Souza, Ning-Yi Wang, Hao Wu, Yen-Hsiang Wang, Mandy Tang, Gabriel Virbila, Mike Pham, Derek Yang, Qun Jane Gu, Yi-Cheng Wu, Yen-Cheng Kuan, Charles Chien, Mau-Chung Frank Chang. 316-318 [doi]
• Power-efficient readout circuit for miniaturized electronic noseVioleta Petrescu, Julia Pettine, Devrez M. Karabacak, Marianne Vandecasteele, Mercedes Crego Calama, Chris Van Hoof. 318-320 [doi]
• Towards ultra-dense arrays of VHF NEMS with FDSOI-CMOS active pixels for sensing applicationsGregory Arndt, Cecilia Dupre, Julien Arcamone, Gerald Cibrario, Olivier Rozeau, Laurent Duraffourg, Eric Ollier, Éric Colinet. 320-322 [doi]
• Session 19 overview: 20+ Gb/s wireline transceivers and injection-locked clocking: Wireline subcommitteeKen Chang, SeongHwan Cho. 322-323 [doi]
• A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technologyJohn F. Bulzacchelli, Troy J. Beukema, Daniel Storaska, Ping-Hsuan Hsieh, Sergey V. Rylov, Daniel Furrer, Daniele Gardellini, Andrea Prati, Christian Menolfi, David Hanson, Juergen Hertle, Thomas Morf, Vivek Sharma, Ram Kelkar, Herschel A. Ainspan, William Kelly, Glenn Ritter, Jon Garlett, Robert Callan, Thomas Toifl, Daniel J. Friedman. 324-326 [doi]
• A 225mW 28Gb/s SerDes in 40nm CMOS with 13dB of analog equalization for 100GBASE-LR4 and optical transport lane 4.4 applicationsMike Harwood, Steffen Nielsen, Andre Szczepanek, Richard Allred, Sean Batty, Mike Case, Simon Forey, Karthik Gopalakrishnan, Larry Kan, Bob Killips, Parmanand Mishra, Rohit Pande, Hamid Rategh, Alan Ren, Jeff Sanders, Albrecht Schoy, Richard Ward, Martin Wetterhorn, Norman Yeung. 326-327 [doi]
• A 40nm CMOS single-chip 50Gb/s DP-QPSK/BPSK transceiver with electronic dispersion compensation for coherent optical channelsDiego E. Crivelli, Mario Rafael Hueda, Hugo S. Carrer, Jeff Zachan, Vadim Gutnik, Martin Del Barco, Ramiro Lopez, Geoff Hatcher, Jorge M. Finochietto, Michael Yeo, Andre Chartrand, Norman Swenson, Paul Voois, Oscar E. Agazzi. 328-330 [doi]
• A dual 23Gb/s CMOS transmitter/receiver chipset for 40Gb/s RZ-DQPSK and CS-RZ-DQPSK optical transmissionDelong Cui, Bharath Raghavan, Ullas Singh, Anand Vasani, Zhi Huang, Deyi Pi, Mehdi Khanpour, Ali Nazemi, Hassan Maarefi, Tamer Ali, Nick Huang, Wei Zhang, Bo Zhang, Afshin Momtaz, Jun Cao. 330-332 [doi]
• A versatile multi-modality serial linkYusuke Tanaka, Yasufumi Hino, Yasuhiro Okada, Takahiro Takeda, Sho Ohashi, Hiroyuki Yamagishi, Kenichi Kawasaki, Ali Hajimiri. 332-334 [doi]
• A 28Gb/s source-series terminated TX in 32nm CMOS SOIChristian Menolfi, Juergen Hertle, Thomas Toifl, Thomas Morf, Daniele Gardellini, Matthias Braendli, Peter Buchmann, Marcel A. Kossel. 334-336 [doi]
• An all-digital clock generator using a fractionally injection-locked oscillator in 65nm CMOSPyoungwon Park, Jaejin Park, Hojin Park, SeongHwan Cho. 336-337 [doi]
• A 2.4GHz sub-harmonically injection-locked PLL with self-calibrated injection timingYi-Chieh Huang, Shen-Iuan Liu. 338-340 [doi]
• Session 20 overview: RF frequency generation: RF subcommitteeRobert Bogdan Staszewski, Taizo Yamawaki. 340-341 [doi]
• A 20Mb/s phase modulator based on a 3.6GHz digital PLL with -36dB EVM at 5mW powerGiovanni Marzin, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita. 342-344 [doi]
• A 14.2mW 2.55-to-3GHz cascaded PLL with reference injection, 800MHz delta-sigma modulator and 255fsrms integrated jitter in 0.13μm CMOSDongmin Park, SeongHwan Cho. 344-346 [doi]
• A 40nm CMOS all-digital fractional-N synthesizer without requiring calibrationFrank Opteynde. 346-347 [doi]
• A 36mW/9mW power-scalable DCO in 55nm CMOS for GSM/WCDMA frequency synthesizersAntonio Liscidini, Luca Fanori, Pietro Andreani, Rinaldo Castello. 348-350 [doi]
• A clip-and-restore technique for phase desensitization in a 1.2V 65nm CMOS oscillator for cellular mobile and base stationsAkshay Visweswaran, Robert Bogdan Staszewski, John R. Long. 350-352 [doi]
• A 32nm CMOS all-digital reconfigurable fractional frequency divider for LO generation in multistandard SoC radios with on-the-fly interference managementKailash Chandrashekar, Stefano Pellerano, Paolo Madoglio, Ashoke Ravi, Yorgos Palaskas. 352-354 [doi]
• A 6.7-to-9.2GHz 55nm CMOS hybrid Class-B/Class-C cellular TX VCOLuca Fanori, Antonio Liscidini, Pietro Andreani. 354-356 [doi]
• Session 21 overview: Analog techniques: Analog subcommitteeJafar Savoj, Chris Mangelsdorf. 356-357 [doi]
• th-order switched gm-C bandpass filter with >55dB ultimate rejection and out-of-band IIP3 of +29dBmMilad Darvishi, Ronan A. R. van der Zee, Eric A. M. Klumperink, Bram Nauta. 358-360 [doi]
• th-order Butterworth filter using ring-oscillator-based integrators in 90nm CMOSBrian Drost, Mrunmay Talegaonkar, Pavan Kumar Hanumolu. 360-362 [doi]
• A 65nm CMOS 1-to-10GHz tunable continuous-time low-pass filter for high-data-rate communicationsFawzi Houfaf, Mathieu Egot, Andreas Kaiser, Andreia Cathelin, Bram Nauta. 362-364 [doi]
• 2 bandgap voltage reference for 1.1V supply in standard 0.16μm CMOSAnne-Johan Annema, George Goksun. 364-366 [doi]
• A 5.58nW 32.768kHz DLL-assisted XO for real-time clocks in wireless sensing applicationsDongmin Yoon, Dennis Sylvester, David Blaauw. 366-368 [doi]
• 2 144μW three-stage amplifier capable of driving 1-to-15nF capacitive load with >0.95MHz GBWZushu Yan, Pui-In Mak, Man Kay Law, Rui Paulo Martins. 368-370 [doi]
• A 90Vpp 720MHz GBW linear power amplifier for ultrasound imaging transmitters in BCD6-SOIDario Bianchi, Fabio Quaglia, Andrea Mazzanti, Francesco Svelto. 370-372 [doi]
• On-chip gain reconfigurable 1.2V 24μW chopping instrumentation amplifier with automatic resistor matching in 0.13μm CMOSFridolin Michel, Michiel Steyaert. 372-374 [doi]
• A capacitively coupled chopper instrumentation amplifier with a ±30V common-mode range, 160dB CMRR and 5μV offsetQinwen Fan, Johan H. Huijsing, Kofi A. A. Makinwa. 374-376 [doi]
• A 60V capacitive gain 27nV/√Hz 137dB CMRR PGA with ±10V inputsChristian Birk, Gerard Mora-Puchalt. 376-377 [doi]
• Session 22 overview: Image sensors: Imagers, MEMS, medical and displays subcommitteeDavid Stoppa, Robert Johansson. 378-379 [doi]
• An 83dB-dynamic-range single-exposure global-shutter CMOS image sensor with in-pixel dual storageMasaki Sakakibara, Yusuke Oike, Takafumi Takatsuka, Akihiko Kato, Katsumi Honda, Tadayuki Taura, Takashi Machida, Jun Okuno, Atsuhiro Ando, Taketo Fukuro, Tomohiko Asatsuma, Suzunori Endo, Junpei Yamamoto, Yasuhiro Nakano, Takumi Kaneshige, Ikuhiro Yamamura, Takayuki Ezaki, Teruo Hirayama. 380-382 [doi]
• A global-shutter CMOS image sensor with readout speed of 1Tpixel/s burst and 780Mpixel/s continuousYasuhisa Tochigi, Katsuhiko Hanzawa, Yuri Kato, Rihito Kuroda, Hideki Mutoh, Ryuta Hirose, Hideki Tominaga, Kenji Takubo, Yasushi Kondo, Shigetoshi Sugawa. 382-384 [doi]
• -rms-temporal-readout-noise CMOS image sensor for low-light-level imagingYue Chen, Yang Xu, Youngcheol Chae, Adri Mierop, Xinyang Wang, Albert Theuwissen. 384-386 [doi]
• A 256×256 CMOS image sensor with ΔΣ-based single-shot compressed sensingYusuke Oike, Abbas El Gamal. 386-388 [doi]
• A 33Mpixel 120fps CMOS image sensor using 12b column-parallel pipelined cyclic ADCsToshihisa Watabe, Kazuya Kitamura, Takehide Sawamoto, Tomohiko Kosugi, Tomoyuki Akahori, Tetsuya Iida, Keigo Isobe, Takashi Watanabe, Hiroshi Shimamoto, Hiroshi Ohtake, Satoshi Aoyama, Shoji Kawahito, Norifumi Egami. 388-390 [doi]
• A 14b extended counting ADC implemented in a 24Mpixel APS-C CMOS image sensorJae-Hong Kim, Wun-ki Jung, Seung-hyun Lim, Yu-jin Park, Won Ho Choi, Yun-jung Kim, Chang-eun Kang, Ji-hun Shin, Kyo-jin Choo, Won-baek Lee, Jin-kyeong Heo, Byung Jo Kim, Se-jun Kim, Min-ho Kwon, Kwi-sung Yoo, Jin-Ho Seo, Seog-heon Ham, Chi-young Choi, Gab-soo Han. 390-392 [doi]
• A 1.5Mpixel RGBZ CMOS image sensor for simultaneous color and range image captureWonjoo Kim, Yibing Wang, Ilia A. Ovsiannikov, Seunghoon Lee, Yoondong Park, Chilhee Chung, Eric R. Fossum. 392-394 [doi]
• A QVGA-range image sensor based on buried-channel demodulator pixels in 0.18μm CMOS with extended dynamic rangeLucio Pancheri, Nicola Massari, Matteo Perenzoni, Mattia Malfatti, David Stoppa. 394-396 [doi]
• A 1920×1080 3.65μm-pixel 2D/3D image sensor with split and binning pixel structure in 0.11pm standard CMOSSeong-Jin Kim, Byongmin Kang, James D. K. Kim, KeeChang Lee, Chang-Yeong Kim, Kinam Kim. 396-398 [doi]
• Session 23 overview: Advances in heterogeneous integration: Technology directions subcommitteeTadahiro Kuroda, David Ruffieux. 398-399 [doi]
• 2Noah Sturcken, Eugene J. O'Sullivan, Naigang Wang, Philipp Herget, Bucknell C. Webb, Lubomyr T. Romankiw, Michele Petracca, Ryan Davies, Robert E. Fontana, Gary M. Decad, Ioannis Kymissis, Angel V. Peterchev, Luca P. Carloni, William J. Gallagher, Kenneth L. Shepard. 400-402 [doi]
• 3 die-stacked sensing platform with optical communication and multi-modal energy harvestingYoonmyung Lee, Gyouho Kim, Suyoung Bang, Yejoong Kim, Inhee Lee, Prabal Dutta, Dennis Sylvester, David Blaauw. 402-404 [doi]
• A DC-isolated gate drive IC with drive-by-microwave technology for power switching devicesShuichi Nagai, Noboru Negoro, Takeshi Fukuda, Nobuyuki Otsuka, Hiroyuki Sakai, Tetsuzo Ueda, Tsuyoshi Tanaka, Daisuke Ueda. 404-406 [doi]
• Nonvolatile 3D-FPGA with monolithically stacked RRAM-based configuration memoryYoung Yang Liauw, Zhiping Zhang, Wanki Kim, Abbas El Gamal, S. Simon Wong. 406-408 [doi]
• Session 24 overview: 10GBase-T and optical front ends: Wireline subcommitteeMiki Moyal, Chewnpu Jou. 408-409 [doi]
• A sub-2W 10GBase-T analog front-end in 40nm CMOS processTarun Gupta, Frank Yang, Dong Wang, Ali Tabatabaei, Ramesh Singh, Hesam Amir Aslanzadeh, Alireza Khalili, Saurabh Vats, Susan Arno, Sean Campeau. 410-412 [doi]
• A 16-port FCC-compliant 10GBase-T transmitter and hybrid with 76dBc SFDR up to 400MHz scalable to 48 portsFriedel Gerfers, Ramin Farjad-Rad, Michael Brown, Ahmad Tavakoli, David Nguyen, Hiok-Tiaq Ng, Ramin Shirani. 412-413 [doi]
• A 10Gb/s burst-mode laser diode driver for burst-by-burst power savingHiroshi Koizumi, Minoru Togashi, Masafumi Nogawa, Yusuke Ohtomo. 414-416 [doi]
• A 10Gb/s burst-mode TIA with on-chip reset/lock CM signaling detection and limiting amplifier with a 75ns settling timeXin Yin, Jasmien Put, Jochen Verbrugghe, Jan Gillis, Xing-Zhi Qiu, Johan Bauwelinck, Jan Vandewege, Heinz-Georg Krimmel, Mohand Achouche. 416-418 [doi]
• 25Gb/s 3.6pJ/b and 15Gb/s 1.37pJ/b VCSEL-based optical links in 90nm CMOSJonathan Proesel, Clint Schow, Alexander Rylyakov. 418-420 [doi]
• Session 25 overview: Non-volatile memory solutions: Memory subcommitteeTadaaki Yamauchi, Satoru Hanzawa. 420-421 [doi]
• 2 64Gb multi-level flash memory with 400Mb/s/pin 1.8V Toggle Mode interfaceNoboru Shibata, Kazushige Kanda, Toshiki Hisada, Katsuaki Isobe, Manabu Sato, Yui Shimizu, Takahiro Shimizu, Takahiro Sugimoto, Tomohiro Kobayashi, K. Inuzuka, Naoaki Kanagawa, Yasuyuki Kajitani, Takeshi Ogawa, J. Nakai, Kiyoaki Iwasa, Masatsugu Kojima, Toshihiro Suzuki, Yuya Suzuki, Shintaro Sakai, Tomofumi Fujimura, Yuko Utsunomiya, Toshifumi Hashimoto, M. Miakashi, Naoki Kobayashi 0004, M. Inagaki, Yuuki Matsumoto, Satoshi Inoue, Yoshinao Suzuki, D. He, Yasuhiko Honda, Junji Musha, Masaki Nakagawa, Mitsuaki Honma, Naofumi Abiko, Mitsumasa Koyanagi, Masahiro Yoshihara, Kazumi Ino, Mitsuhiro Noguchi, Teruhiko Kamei, Yosuke Kato, Shingo Zaitsu, Hiroaki Nasu, T. Ariki, Hardwell Chibvongodze, Mitsuyuki Watanabe, Hong Ding, Naoki Ookuma, Ryuji Yamashita, G. Liang, Gertjan Hemink, Farookh Moogat, Cuong Trinh, Masaaki Higashitani, Tuan Pham, K. Kanazawa. 422-424 [doi]
• 2 64Gb multi-level flash memory with 400Mb/s/pin 1.8V Toggle Mode interfaceNoboru Shibata, Kazushige Kanda, Toshiki Hisada, Katsuaki Isobe, Manabu Sato, Yui Shimizu, Takahiro Shimizu, Takahiro Sugimoto, Tomohiro Kobayashi, K. Inuzuka, Naoaki Kanagawa, Yasuyuki Kajitani, Takeshi Ogawa, J. Nakai, Kiyoaki Iwasa, Masatsugu Kojima, Toshihiro Suzuki, Yuya Suzuki, Shintaro Sakai, Tomofumi Fujimura, Yuko Utsunomiya, Toshifumi Hashimoto, M. Miakashi, Naoki Kobayashi 0004, M. Inagaki, Yuuki Matsumoto, Satoshi Inoue, Yoshinao Suzuki, D. He, Yasuhiko Honda, Junji Musha, M. Nakagawa, Mitsuaki Honma, Naofumi Abiko, Mitsumasa Koyanagi, Masahiro Yoshihara, Kazumi Ino, Mitsuhiro Noguchi, Teruhiko Kamei, Yosuke Kato, Shingo Zaitsu, Hiroaki Nasu, T. Ariki, Hardwell Chibvongodze, Mitsuyuki Watanabe, Hong Ding, Naoki Ookuma, Ryuji Yamashita, G. Liang, Gertjan Hemink, Farookh Moogat, Cuong Trinh, Masaaki Higashitani, Tuan Pham, K. Kanazawa. 422-424 [doi]
• Over-10×-extended-lifetime 76%-reduced-error solid-state drives (SSDs) with error-prediction LDPC architecture and error-recovery schemeShuhei Tanakamaru, Yuki Yanagihara, Ken Takeuchi. 424-426 [doi]
• 6.4Gb/s multi-threaded BCH encoder and decoder for multi-channel SSD controllersYoungjoo Lee, Hoyoung Yoo, Injae Yoo, In-Cheol Park. 426-428 [doi]
• Bitline-capacitance-cancelation sensing scheme with 11ns read latency and maximum read throughput of 2.9GB/s in 65nm embedded flash for automotiveMihail Jefremow, Thomas Kern, Ulrich Backhausen, Christian Peters, Christoph Parzinger, Christoph Roll, Stephan Kassenetter, Stefanie Thierold, Doris Schmitt-Landsiedel. 428-430 [doi]
• A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technologyDaeyeal Lee, Ik Joon Chang, Sangyong Yoon, Joonsuc Jang, Dong-Su Jang, Wook-Ghee Hahn, Jong-Yeol Park, Doo-Gon Kim, Chiweon Yoon, Bong-Soon Lim, ByungJun Min, Sung-Won Yun, Ji-Sang Lee, Il Han Park, Kyung-Ryun Kim, Jeong-Yun Yun, Youse Kim, Yong-Sung Cho, Kyung-Min Kang, Sang-Hyun Joo, Jin-Young Chun, Jung-No Im, Seunghyuk Kwon, Seokjun Ham, AnSoo Park, Jae-Duk Yu, Nam Hee Lee, Tae-Sung Lee, Moosung Kim, Hoosung Kim, Ki-Whan Song, Byung-gil Jeon, Kihwan Choi, Jin-Man Han, Kyehyun Kyung, Youngho Lim, Young-Hyun Jun. 430-432 [doi]
• An 8Mb multi-layered cross-point ReRAM macro with 443MB/s write throughputAkifumi Kawahara, Ryotaro Azuma, Yuuichirou Ikeda, Ken Kawai, Yoshikazu Katoh, Kouhei Tanabe, Toshihiro Nakamura, Yoshihiko Sumimoto, Naoki Yamada, Nobuyuki Nakai, Shoji Sakamoto, Yukio Hayakawa, Kiyotaka Tsuji, Shinichi Yoneda, Atsushi Himeno, Ken-ichi Origasa, Kazuhiko Shimakawa, Takeshi Takagi, Takumi Mikawa, Kunitoshi Aono. 432-434 [doi]
• A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read timeMeng-Fan Chang, Che-Wei Wu, Chia-Chen Kuo, Shin-Jang Shen, Ku-Feng Lin, Shu-Meng Yang, Ya-Chin King, Chorng-Jung Lin, Yu-Der Chih. 434-436 [doi]
• 128Gb 3b/cell NAND flash memory in 19nm technology with 18MB/s write rate and 400Mb/s toggle modeYan Li, Seungpil Lee, Ken Oowada, Hao Nguyen, Qui Nguyen, Nima Mokhlesi, Cynthia Hsu, Jason Li, Venky Ramachandra, Teruhiko Kamei, Masaaki Higashitani, Tuan Pham, Mitsuaki Honma, Yoshihisa Watanabe, Kazumi Ino, Binh Le, Byungki Woo, Khin Htoo, Taiyuan Tseng, Long Pham, Frank Tsai, Kwang Ho Kim, Yi-Chieh Chen, Min She, Jonghak Yuh, Alex Chu, Chen Chen, Ruchi Puri, Hung-Szu Lin, Yi Fang Chen, William Mak, Jonathan Huynh, Jim Chan, Mitsuyuki Watanabe, Daniel Yang, Grishma Shah, Pavithra Souriraj, Dinesh Tadepalli, Tenugu Suman, Ray Gao, Viski Popuri, Behdad Azarbayjani, Ravindra Madpur, James Lan, Emilio Yero, Feng Pan, Patrick Hong, Jang Yong Kang, Farookh Moogat, Yupin Fong, Raul Cernea, Sharon Huynh, Cuong Trinh, Mehrdad Mofidi, Ritu Shrivastava, Khandker Quader. 436-437 [doi]
• 128Gb 3b/cell NAND flash memory in 19nm technology with 18MB/s write rate and 400Mb/s toggle modeYan Li, Seungpil Lee, Ken Oowada, Hao Nguyen, Qui Nguyen, Nima Mokhlesi, Cynthia Hsu, Jason Li, Venky Ramachandra, Teruhiko Kamei, Masaaki Higashitani, Tuan Pham, Mitsuaki Honma, Yoshihisa Watanabe, Kazumi Ino, Binh Le, Byungki Woo, Khin Htoo, Taiyuan Tseng, Long Pham, Frank Tsai, Kwang Ho Kim, Yi-Chieh Chen, Min She, Jonghak Yuh, Alex Chu, Chen Chen, Ruchi Puri, Hung-Szu Lin, Yi Fang Chen, William Mak, Jonathan Huynh, Jim Chan, Mitsuyuki Watanabe, Daniel Yang, Grishma Shah, Pavithra Souriraj, Dinesh Tadepalli, Tenugu Suman, Ray Gao, Viski Popuri, Behdad Azarbayjani, Ravindra Madpur, James Lan, Emilio Yero, Feng Pan, Patrick Hong, Jang Yong Kang, Farookh Moogat, Yupin Fong, Raul Cernea, Sharon Huynh, Cuong Trinh, Mehrdad Mofidi, Ritu Shrivastava, Khandker Quader. 436-437 [doi]
• Session 26 overview: Short-range wireless transceivers: Wireless subcommitteeRanjit Gharpurey, Woogeun Rhee. 438-439 [doi]
• A 1V 357Mb/s-throughput transferjet™ SoC with embedded transceiver and digital baseband in 90nm CMOSMasahisa Tamura, Fumitaka Kondo, Katsumi Watanabe, Yasunori Aoki, Yusuke Shinohe, Koki Uchino, Yuhei Hashimoto, Fumihiro Nishiyama, Hiroaki Miyachi, Ikuho Nagase, Itaru Uezono, Rie Hisamura, Itaru Maekawa. 440-442 [doi]
• A 2Gb/s 150mW UWB direct-conversion coherent transceiver with IQ-switching carrier recovery schemeTakayuki Abe, Yuxiang Yuan, Hiroki Ishikuro, Tadahiro Kuroda. 442-444 [doi]
• 3-to-5GHz 4-channel UWB beamforming transmitter with 1° phase resolution through calibrated vernier delay line in 0.13μm CMOSLei Wang, Yongxin Guo, Yong Lian, Chun-Huat Heng. 444-446 [doi]
• An interference-aware 5.8GHz wake-up radio for ETCSJeongki Choi, Kanghyuk Lee, Seok-Oh Yun, Sang-Gug Lee, Jinho Ko. 446-448 [doi]
• A 2.7nJ/b multi-standard 2.3/2.4GHz polar transmitter for wireless sensor networksYao-Hong Liu, Xiongchuan Huang, Maja Vidojkovic, Koji Imamura, Pieter Harpe, Guido Dolmans, Harmke de Groot. 448-450 [doi]
• A meter-range UWB transceiver chipset for around-the-head audio streamingXiaoyan Wang, Yikun Yu, Benjamin Busze, Hans Pflug, Alex Young, Xiongchuan Huang, Cui Zhou, Mario Konijnenburg, Kathleen Philips, Harmke de Groot. 450-452 [doi]
• A 90nm CMOS 5Mb/s crystal-less RF transceiver for RF-powered WSN nodesGiuseppe Papotto, Francesco Carrara, Alessandro Finocchiaro, Giuseppe Palmisano. 452-454 [doi]
• A 915MHz 120μW-RX/900μW-TX envelope-detection transceiver with 20dB in-band interference toleranceXiongchuan Huang, Ao Ba, Pieter Harpe, Guido Dolmans, Harmke de Groot, John R. Long. 454-456 [doi]
• Session 27 overview: Data converter techniques: Data converters subcommitteeDieter Draxelmayr, Takahiro Miki. 456-457 [doi]
• A 14b 3/6GHz current-steering RF DAC in 0.18μm CMOS with 66dB ACLR at 2.9GHzGil Engel, Shawn Kuo, Steve Rose. 458-460 [doi]
• Ring amplifiers for switched-capacitor circuitsBenjamin P. Hershberg, Skyler Weaver, Kazuki Sobue, Seiji Takeuchi, Koichi Hamashita, Un-Ku Moon. 460-462 [doi]
• A 5.37mW 10b 200MS/s dual-path pipelined ADCYun Chai, Jieh-Tsorng Wu. 462-464 [doi]
• A 13b 315fsrms 2mW 500MS/s 1MHz bandwidth highly digital time-to-digital converter using switched ring oscillatorsAmr Elshazly, Sachin Rao, Brian Young, Pavan Kumar Hanumolu. 464-466 [doi]
• A 1.7mW 11b 250MS/s 2× interleaved fully dynamic pipelined SAR ADC in 40nm digital CMOSBob Verbruggen, Masao Iriguchi, Jan Craninckx. 466-468 [doi]
• A 90MS/s 11MHz bandwidth 62dB SNDR noise-shaping SAR ADCJeffrey Fredenburg, Michael P. Flynn. 468-470 [doi]
• A 70dB DR 10b 0-to-80MS/s current-integrating SAR ADC with adaptive dynamic rangeBadr Malki, Takaya Yamamoto, Bob Verbruggen, Piet Wambacq, Jan Craninckx. 470-472 [doi]
• A 7-to-10b 0-to-4MS/s flexible SAR ADC with 6.5-to-16fJ/conversion-stepPieter Harpe, Yan Zhang, Guido Dolmans, Kathleen Philips, Harmke de Groot. 472-474 [doi]
• A 31.3fJ/conversion-step 70.4dB SNDR 30MS/s 1.2V two-step pipelined ADC in 0.13μm CMOSHo-Young Lee, Bumha Lee, Un-Ku Moon. 474-476 [doi]
• Session 28 overview: Adaptive and low-power circuits: Energy-efficient digital subcommitteeMichael Phan, Masaya Sumita. 476-477 [doi]
• A 4.5Tb/s 3.4Tb/s/W 64×64 switch fabric with self-updating least-recently-granted priority and quality-of-service arbitration in 45nm CMOSSudhir Satpathy, Korey Sewell, Thomas Manville, Yen-Po Chen, Ronald G. Dreslinski, Dennis Sylvester, Trevor N. Mudge, David Blaauw. 478-480 [doi]
• A 1.0TOPS/W 36-core neocortical computing processor with 2.3Tb/s Kautz NoC for universal visual recognitionChuan-Yung Tsai, Yu-Ju Lee, Chun-Ting Chen, Liang-Gee Chen. 480-482 [doi]
• Conditional push-pull pulsed latches with 726fJ·ps energy-delay product in 65nm CMOSElio Consoli, Massimo Alioto, Gaetano Palumbo, Jan M. Rabaey. 482-484 [doi]
• A 200mV 32b subthreshold processor with adaptive supply voltage controlSven Lütkemeier, Thorsten Jungeblut, Mario Porrmann, Ulrich Rückert. 484-486 [doi]
• 13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDOKoji Hirairi, Yasuyuki Okuma, Hiroshi Fuketa, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai. 486-488 [doi]
• Bubble Razor: An architecture-independent approach to timing-error detection and correctionMatthew Fojtik, David Fick, Yejoong Kim, Nathaniel Ross Pinckney, David Money Harris, David Blaauw, Dennis Sylvester. 488-490 [doi]
• A 25MHz 7μW/MHz ultra-low-voltage microcontroller SoC in 65nm LP/GP CMOS for low-carbon wireless sensor nodesDavid Bol, Julien De Vos, Cédric Hocquet, François Botman, François Durvaux, Sarah Boyd, Denis Flandre, Jean-Didier Legat. 490-492 [doi]
• A 530mV 10-lane SIMD processor with variation resiliency in 45nm SOIRobert Pawlowski, Evgeni Krimer, Joseph Crop, Jacob Postman, Nariman Moezzi Madani, Mattan Erez, Patrick Chiang. 492-494 [doi]
• Beamforming techniques and RF transceiver designEric A. M. Klumperink, Domine Leenaerts, Gabriel M. Rebeiz. 498-499 [doi]
• Robust VLSI circuit design & systems for sustainable societyKen Takeuchi, Jan Crols, Ken Takeuchi, Jan Crols, Kevin Zhang, Mike Clinton, Tadaaki Yamauchi. 500-501 [doi]
• 10-40 Gb/s I/O design for data communicationsKen Chang, Tony Chan Carusone, Ali Sheikholeslami, Bob Payne, Miki Moyal, John Stonick, Hisakatsu Yamaguchi. 502-503 [doi]
• Computational imagingMakoto Ikeda, Albert Theuwissen, Johannes Solhusvik, Jan T. Bosiers, Makoto Ikeda. 504-505 [doi]
• Bioelectronics for sustainable healthcareChris Van Hoof, Wim Dehaene, Wentai Liu, Wim Dehaene, Timothy Denison, Minkyu Je, Wentai Liu, Chris Van Hoof, Hoi-Jun Yoo. 506-507 [doi]
• Power/performance optimization of many-core processor SoCsStephen Kosonocky, Vladimir Stojanovic, Kees van Berkel, Ming-Yang Chao, Tobias Knoll, Joshua Friedrich. 508-509 [doi]
• Is RF doomed to digitization? What shall RF circuit designers do?Robert Bogdan Staszewski, Jacques C. Rudell. 510 [doi]
• Little-known features of well-known creaturesUn-Ku Moon, Shanthi Pavan. 511 [doi]
• What is the next RF frontier?Gangadhar Burra, Hossein Hashimi. 512 [doi]
• What's next in robots? ∼Sensing, processing, networking toward human brain and bodyKazutami Arimoto, Sam Kavusi, Kenneth Salisbury. 514 [doi]
• Technologies that could change the world - You decide!Jed Hurwitz, Jafar Savoj. 515 [doi]
• Optical PCB interconnects, Niche or mainstream?Ichiro Fujimori, SeongHwan Cho, Joshua Friedrich, John Stonick. 516 [doi]
• Vision for future televisionAtsuki Inoue, Masaitsu Nakajima. 517 [doi]
• Low-power analog signal processingWilly Sansen, Christian Enz, Willy Sansen, Boris Murmann, Philip K. T. Mok. 518 [doi]