Matt Wordeman, Joel Silberman, Gary Maier, Michael Scheuermann. A 3D system prototype of an eDRAM cache stacked over processor-like logic using through-silicon vias. In 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012, San Francisco, CA, USA, February 19-23, 2012. pages 186-187, IEEE, 2012. [doi]
Abstract is missing.