Yusuke Ohtomo - researchr alias

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Viewing Publication 1 - 26 from 26

2015

DD CMOS/SIMOX TechniquesNobutaro Shibata, Yusuke Ohtomo, Mika Nishisaka, Yasuhiro Sato. tvlsi, 23(6):1089-1102, 2015. [doi]

2013

2012

2011

An Injection-Controlled 10-Gb/s Burst-Mode CDR Circuit for a 1G/10G PON SystemHiroaki Katsurai, Hideki Kamitsuna, Hiroshi Koizumi, Jun Terada, Yusuke Ohtomo, Tsugumichi Shibata. ieicet, 94-C(4):582-588, 2011. [doi]

Bandwidth enhancement for high speed amplifier utilizing mutually coupled on-chip inductorsAkira Tsuchiya, Takeshi Kuboki, Yusuke Ohtomo, Keiji Kishine, Shigekazu Miyawaki, Makoto Nakamura, Hidetoshi Onodera. isocc 2011: 36-39 [doi]

2010

A 16Gbps laser-diode driver with interwoven peaking inductors in 0.18-µm CMOSTakeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera. cicc 2010: 1-4 [doi]

2009

Jitter-reduction and pulse-width-distortion compensation circuits for a 10Gb/s burst-mode CDR circuitJun Terada, Yusuke Ohtomo, Kazuyoshi Nishimura, Hiroaki Katsurai, Shunji Kimura, Naoto Yoshimoto. isscc 2009: 104-105 [doi]

2008

A 1ps-Resolution 2ns-Span 10Gb/s Data-Timing Generator with Spectrum ConversionTomoaki Kawamura, Yusuke Ohtomo, Kazuyoshi Nishimura, Noboru Ishihara. isscc 2008: 456-457 [doi]

A PVT Tolerant STM-16 Clock-and-Data Recovery LSI Using an On-Chip Loop-Gain Variation Compensation Architecture in 0.20-µm CMOS/SOIYusuke Ohtomo, Hiroshi Koizumi, Kazuyoshi Nishimura, Masafumi Nogawa. ieicet, 91-C(4):655-661, 2008. [doi]

A 10-Gb/s Burst-Mode Clock-and-Data Recovery IC with Frequency-Adjusting Dual Gated VCOsYusuke Ohtomo, Masafumi Nogawa, Kazuyoshi Nishimura, Shunji Kimura, Tomoaki Yoshida, Tomoaki Kawamura, Minoru Togashi, Kiyomi Kumozaki. ieicet, 91-C(6):903-910, 2008. [doi]

A wide range, over 9.6ns, skew compensation LSI for a flexible optical access systemYoshihito Sakai, Hideaki Kimura, Yusuke Ohtomo, Makoto Tsubokawa. ieiceee, 5(4):157-162, 2008. [doi]

A 10.3125Gb/s Burst-Mode CDR Circuit using a δσ DACJun Terada, Kazuyoshi Nishimura, Shunji Kimura, Hiroaki Katsurai, Naoto Yoshimoto, Yusuke Ohtomo. isscc 2008: 226-227 [doi]

A 10.3 Gb/s Burst-Mode CDR Using a ΔΣ DACJun Terada, Kazuyoshi Nishimura, Shunji Kimura, Hiroaki Katsurai, Naoto Yoshimoto, Yusuke Ohtomo. jssc, 43(12):2921-2928, 2008. [doi]

2007

SE3 Last Mile Access Options: PON/DSL/Cable/WirelessLarry DeVito, Yusuke Ohtomo. isscc 2007: 144-145 [doi]

High sensitivity APD burst-mode receiver for 10Gbit/s TDM-PON systemTakashi Nakanishi, Ken-ichi Suzuki, Youichi Fukada, Naoto Yoshimoto, Makoto Nakamura, Kazutoshi Kato, Kazuyoshi Nishimura, Yusuke Ohtomo, Makoto Tsubokawa. ieiceee, 4(19):588-592, 2007. [doi]

2006

A 10Gb/s burst-mode adaptive gain select limiting amplifier in 0.13µm CMOSMasafumi Nogawa, Yusuke Ohtomo, Shunji Kimura, Kazuyoshi Nishimura, Tomoaki Kawamura, Minoru Togashi. isscc 2006: 940-949 [doi]

A 12.5-Gb/s Parallel Phase Detection Clock and Data Recovery Circuit in 0.13-$muhbox m$CMOSYusuke Ohtomo, Kazuyoshi Nishimura, Masafumi Nogawa. jssc, 41(9):2052-2057, 2006. [doi]

1999

A 10-Gb/s (1.25 Gb/s/spl times/8)4/spl times/2 0.25-μm CMOS/SIMOX ATM switch based on scalable distributed arbitrationEiji Oki, Naoaki Yamanaka, Yusuke Ohtomo, Kazuhiko Okazaki, Ryusuke Kawano. jssc, 34(12):1921-1934, 1999. [doi]

1998

A data-transition look-ahead DFF circuit for statistical reduction in power consumptionMasafumi Nogawa, Yusuke Ohtomo. jssc, 33(5):702-706, 1998. [doi]

1994

BiCMOS circuit technology for a 704 MHz ATM switch LSIYusuke Ohtomo, Sadayuki Yasuda, Minoru Togashi, Massyuki Ino, Yasuyuki Tanabe, Jun-ichi Inoue, Masafumi Nogawa, Sshigeki Hino. jssc, 29(5):557-563, May 1994. [doi]

1992

A 250-Mb/s, 700-mW, 32-highway*8-b S/P converter LSI with cross-access memoryYusuke Ohtomo, Masao Suzuki. jssc, 27(4):530-538, April 1992. [doi]

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