Table of Contents

• Equivalent circuit model extraction for interconnects in 3D ICsA. Ege Engin. 1-6 [doi]
• Unconditionally stable explicit method for the fast 3-D simulation of on-chip power distribution network with through silicon viaTadatoshi Sekine, Hideki Asai. 7-12 [doi]
• Signal integrity modeling and measurement of TSV in 3D ICJoohee Kim, Joungho Kim. 13-16 [doi]
• Power distribution network modeling for 3-D ICs with TSV arraysChi-Kai Shen, Yi-Chang Lu, Yih-Peng Chiou, Tai-Yu Cheng, Tzong-Lin Wu. 17-22 [doi]
• A case for wireless 3D NoCs for CMPsHiroki Matsutani, Paul Bogdan, Radu Marculescu, Yasuhiro Take, Daisuke Sasaki, Hao Zhang, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano. 23-28 [doi]
• Deflection routing in 3D Network-on-Chip with TSV serializationJinho Lee, Dongwook Lee, Sunwook Kim, Kiyoung Choi. 29-34 [doi]
• MD: Minimal path-based fault-tolerant routing in on-Chip NetworksMasoumeh Ebrahimi, Masoud Daneshtalab, Juha Plosila, Farhad Mehdipour. 35-40 [doi]
• A dynamic stream link for efficient data flow control in NoC based heterogeneous MPSoCClaude Helmstetter, Sylvain Basset, Romain Lemaire, Fabien Clermidy, Pascal Vivet, Michel Langevin, Chuck Pilkington, Pierre G. Paulin, Didier Fuin. 41-46 [doi]
• On real-time STM concurrency control for embedded software with improved schedulabilityMohammed El-Shambakey, Binoy Ravindran. 47-52 [doi]
• Schedule integration for time-triggered systemsFlorian Sagstetter, Martin Lukasiewycz, Samarjit Chakraborty. 53-58 [doi]
• Online estimation of the remaining energy capacity in mobile systems considering system-wide power consumption and battery characteristicsDonghwa Shin, Kitae Kim, Naehyuck Chang, Woojoo Lee, Yanzhi Wang, Qing Xie, Massoud Pedram. 59-64 [doi]
• WUCC: Joint WCET and Update Conscious Compilation for cyber-physical systemsYazhi Huang, Mengying Zhao, Chun Jason Xue. 65-70 [doi]
• A 40-nm 144-mW VLSI processor for real-time 60-kWord continuous speech recognitionGuangji He, Takanobu Sugahara, Tsuyoshi Fujinaga, Yuki Miyamoto, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto. 71-72 [doi]
• A 24.5-53.6pJ/pixel 4320p 60fps H.264/AVC intra-frame video encoder chip in 65nm CMOSDajiang Zhou, Gang He, Wei Fei, Zhixiang Chen, Jinjia Zhou, Satoshi Goto. 73-74 [doi]
• A low power multimedia processor implementing dynamic voltage and frequency scaling techniqueTadayoshi Enomoto, Nobuaki Kobayashi. 75-76 [doi]
• A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation techniqueShusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto. 77-78 [doi]
• A physical unclonable function chip exploiting load transistors' variation in SRAM bitcellsShunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto. 79-80 [doi]
• Over 10-times high-speed, energy efficient 3D TSV-integrated hybrid ReRAM/MLC NAND SSD by intelligent data fragmentation suppressionChao Sun, Hiroki Fujii, Kousuke Miyaji, Koh Johguchi, Kazuhide Higuchi, Ken Takeuchi. 81-82 [doi]
• Highly reliable solid-state drives (SSDs) with error-prediction LDPC (EP-LDPC) architecture and error-recovery schemeShuhei Tanakamaru, Yuki Yanagihara, Ken Takeuchi. 83-84 [doi]
• 2 100b error-correcting BCH decoder in 0.13µm CMOS processYoungjoo Lee, Hoyoung Yoo, In-Cheol Park. 85-86 [doi]
• A 6.72-Gb/s, 8pJ/bit/iteration WPAN LDPC decoder in 65nm CMOSZhixiang Chen, Xiao Peng, Xiongxin Zhao, Leona Okamura, Dajiang Zhou, Satoshi Goto. 87-88 [doi]
• A 7.5Gb/s referenceless transceiver for UHDTV with adaptive equalization and bandwidth scanning technique in 0.13µm CMOS processJunyoung Song, Hyun-Woo Lee, Sewook Hwang, Inhwa Jung, Chulwoo Kim. 89-90 [doi]
• A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched Transmission Line Couplers and Dicode partial-response channel transceiversAtsutake Kosuge, Wataru Mizuhara, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda. 91-92 [doi]
• 315MHz OOK transceiver with 38-µW receiver and 36-µW transmitter in 40-nm CMOSShunta Iguchi, Akira Saito, Kentaro Honda, Yun Fei Zheng, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya. 93-94 [doi]
• A full 4-channel 60 GHz direct-conversion transceiverSeitaro Kawai, Ryo Minami, Ahmed Musa, Takahiro Sato, Ning Li, Tatsuya Yamaguchi, Yasuaki Takeuchi, Yuuki Tsukui, Kenichi Okada, Akira Matsuzawa. 95-96 [doi]
• A sub-harmonic injection-locked frequency synthesizer with frequency calibration scheme for use in 60GHz TDD transceiversTeerachot Siriburanon, Wei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa. 97-98 [doi]
• A fractional-N harmonic injection-locked frequency synthesizer with 10MHz-6.6GHz quadrature outputs for software-defined radiosWei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa. 99-100 [doi]
• A ring-VCO-based sub-sampling PLL CMOS circuit with 0.73 ps jitter and 20.4 mW power consumptionKenta Sogo, Akihiro Toya, Takamaro Kikkawa. 101-102 [doi]
• Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edgesKiichi Niitsu, Naohiro Harigai, Daiki Hirabayashi, Daiki Oki, Masato Sakurai, Osamu Kobayashi, Takahiro J. Yamaguchi, Haruo Kobayashi. 103-104 [doi]
• A 25-Gb/s LD driver with area-effective inductor in a 0.18-µm CMOSTakeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera. 105-106 [doi]
• A regulated charge pump with low-power integrated optimum power point tracking algorithm for indoor solar energy harvestingJungmoon Kim, Chulwoo Kim. 107-108 [doi]
• A low voltage buck DC-DC converter using on-chip gate boost technique in 40nm CMOSXin Zhang, Po-Hung Chen, Yoshikatsu Ryu, Koichi Ishida, Yasuyuki Okuma, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya. 109-110 [doi]
• A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ADCKentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro. 111-112 [doi]
• Thermal management for dependable on-chip systemsJörg Henkel, Thomas Ebi, Hussam Amrouch, Heba Khdr. 113-118 [doi]
• Dependable VLSI Platform using Robust FabricsHidetoshi Onodera. 119-124 [doi]
• Variability-aware memory management for nanoscale computingNikil Dutt, Puneet Gupta, Alex Nicolau, Luis Angel D. Bathen, Mark Gottscho. 125-132 [doi]
• MIXSyn: An efficient logic synthesis methodology for mixed XOR-AND/OR dominated circuitsLuca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli. 133-138 [doi]
• Optimizing multi-level combinational circuits for generating random bitsChen Wang, Weikang Qian. 139-144 [doi]
• Improving the mapping of reversible circuits to quantum circuits using multiple target linesRobert Wille, Mathias Soeken, Christian Otterstedt, Rolf Drechsler. 145-150 [doi]
• I-LUTSim: An iterative look-up table based thermal simulator for 3-D ICsChi-Wen Pan, Yu-Min Lee, Pei-Yu Huang, Chi-Ping Yang, Chang-Tzu Lin, Chia-Hsin Lee, Yung-Fa Chou, Ding-Ming Kwai. 151-156 [doi]
• Compact nonlinear thermal modeling of packaged integrated systemsZao Liu, Sheldon X.-D. Tan, Hai Wang, Sahana Swarup, Ashish Gupta 0007. 157-162 [doi]
• A multilevel ℌ-matrix-based approximate matrix inversion algorithm for vectorless power grid verificationWei Zhao, Yici Cai, Jianlei Yang. 163-168 [doi]
• Realization of frequency-domain circuit analysis through random walkTetsuro Miyakawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato. 169-174 [doi]
• A separation and minimum wire length constrained maze routing algorithm under nanometer wiring rulesFong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak, Sheng-Hsiung Chen. 175-180 [doi]
• An ILP-based automatic bus planner for dense PCBsPei-Ci Wu, Qiang Ma 0002, Martin D. F. Wong. 181-186 [doi]
• Layer minimization in escape routing for staggered-pin-array PCBsYuan-Kai Ho, Xin-Wei Shih, Yao-Wen Chang, Chung-Kuan Cheng. 187-192 [doi]
• Network flow modeling for escape routing on staggered pin arraysPei-Ci Wu, Martin D. F. Wong. 193-198 [doi]
• A clique-based approach to find binding and scheduling result in flow-based microfluidic biochipsTrung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho, Yuko Hara-Azumi. 199-204 [doi]
• Control synthesis for the flow-based microfluidic large-scale integration biochipsWajid Hassan Minhass, Paul Pop, Jan Madsen, Tsung-Yi Ho. 205-212 [doi]
• A network-flow based valve-switching aware binding algorithm for flow-based microfluidic biochipsKai-Han Tseng, Sheng-Chi You, Wajid Hassan Minhass, Tsung-Yi Ho, Paul Pop. 213-218 [doi]
• Design and verification tools for continuous fluid flow-based microfluidic devicesJeffrey McDaniel, Auralila Baez, Brian Crites, Aditya Tammewar, Philip Brisk. 219-224 [doi]
• Optimal partition with block-level parallelization in C-to-RTL synthesis for streaming applicationsShuangchen Li, Yongpan Liu, Xiaobo Sharon Hu, Xinyu He, Yining Zhang, Pei Zhang, Huazhong Yang. 225-230 [doi]
• Multi-mode pipelined MPSoCs for streaming applicationsHaris Javaid, Daniel Witono, Sri Parameswaran. 231-236 [doi]
• Network simplex method based Multiple Voltage Scheduling in Power-efficient High-level synthesisCong Hao, Song Chen, Takeshi Yoshimura. 237-242 [doi]
• VISA synthesis: Variation-aware Instruction Set Architecture synthesisYuko Hara-Azumi, Takuya Azumi, Nikil D. Dutt. 243-248 [doi]
• L-shape based layout fracturing for e-beam lithographyBei Yu, Jhih-Rong Gao, David Z. Pan. 249-254 [doi]
• High-throughput electron beam direct writing of VIA layers by character projection using character sets based on one-dimensional VIA arrays with area-efficient stencil designRimon Ikeno, Takashi Maruyama, Tetsuya Iizuka, Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada. 255-260 [doi]
• Linear time algorithm to find all relocation positions for EUV defect mitigationYuelin Du, Hongbo Zhang, Qiang Ma 0002, Martin D. F. Wong. 261-266 [doi]
• Self-Aligned Double and Quadruple Patterning-aware grid routing with hotspots controlChikaaki Kodama, Hirotaka Ichikawa, Koichi Nakayama, Toshiya Kotani, Shigeki Nojima, Shoji Mimotogi, Shinji Miyamoto, Atsushi Takahashi. 267-272 [doi]
• Compiler-assisted refresh minimization for volatile STT-RAM cacheQing'an Li, Jianhua Li, Liang Shi, Chun Jason Xue, Yiran Chen, Yanxiang He. 273-278 [doi]
• Curling-PCM: Application-specific wear leveling for phase change memory based embedded systemsDuo Liu, Tianzheng Wang, Yi Wang 0003, Zili Shao, Qingfeng Zhuge, Edwin Hsing-Mean Sha. 279-284 [doi]
• Selectively protecting error-correcting code for area-efficient and reliable STT-RAM cachesJunwhan Ahn, Sungjoo Yoo, Kiyoung Choi. 285-290 [doi]
• Loadsa: A yield-driven top-down design method for STT-RAM arrayWujie Wen, Yaojun Zhang, Lu Zhang, Yiran Chen. 291-296 [doi]
• Fractal video compression in OpenCL: An evaluation of CPUs, GPUs, and FPGAs as acceleration platformsDoris Chen, Deshanand P. Singh. 297-304 [doi]
• High-level synthesis of multiple dependent CUDA kernels on FPGASwathi T. Gurumani, Hisham Cholakkal, Yun Liang, Kyle Rupnow, Deming Chen. 305-312 [doi]
• The Liquid Metal IP bridgePerry Cheng, Stephen J. Fink, Rodric M. Rabbah, Sunil Shukla. 313-319 [doi]
• TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCsMohammad Shihabul Haque, Akash Kumar, Yajun Ha, Qiang Wu, Shaobo Luo. 320-325 [doi]
• Optimizing translation information management in NAND flash memory storage systemsQi Zhang, Xuandong Li, Linzhang Wang, Tian Zhang, Yi Wang 0003, Zili Shao. 326-331 [doi]
• An adaptive filtering mechanism for energy efficient data prefetchingXianglei Dang, Xiaoyin Wang, Dong Tong, Zichao Xie, Lingda Li, Keyi Wang. 332-337 [doi]
• Cache Capacity Aware Thread Scheduling for Irregular Memory Access on many-core GPGPUsHsien-Kai Kuo, Ta-Kan Yen, Bo-Cheng Charles Lai, Jing-Yang Jou. 338-343 [doi]
• Optimization of overdrive signoffTuck Boon Chan, Andrew B. Kahng, Jiajia Li, Siddhartha Nath. 344-349 [doi]
• Mountain-mover: An intuitive logic shifting heuristic for improving timing slack violating pathsXing Wei, Wai-Chung Tang, Yu-Liang Wu, Cliff C. N. Sze, Charles J. Alpert. 350-355 [doi]
• Pulsed-latch ASIC synthesis in industrial design flowSangmin Kim, Duckhwan Kim, Youngsoo Shin. 356-361 [doi]
• Power optimization for application-specific 3D network-on-chip with multiple supply voltagesKan Wang, Sheqin Dong. 362-367 [doi]
• Hardware security strategies exploiting nanoelectronic circuitsGarrett S. Rose, Jeyavijayan Rajendran, Nathan R. McDonald, Ramesh Karri, Miodrag Potkonjak, Bryant T. Wysocki. 368-372 [doi]
• Can we identify smartphone app by power trace? [Extended abstract for special session]Mian Dong, Po-Hsiang Lai, Zhu Li. 373-375 [doi]
• Secure storage system and key technologiesJiwu Shu, Zhirong Shen, Wei Xue, Yingxun Fu. 376-383 [doi]
• Mobile user classification and authorization based on gesture usage recognitionKent W. Nixon, Xiang Chen, Zhi-Hong Mao, Yiran Chen, Kang Li. 384-389 [doi]
• Challenges in integration of diverse functionalities on CMOSKazuya Masu, Noboru Ishihara, Toshifumi Konishi, Katsuyuki Machida, Hiroshi Toshiyoshi. 390-393 [doi]
• 3DIC from concept to realityFrank Lee, Bill Shen, Willy Chen, Suk Lee. 394-398 [doi]
• 2.5D design methodologyShinya Tokunaga. 399-402 [doi]
• Design issues in heterogeneous 3D/2.5D integrationDragomir Milojevic, Pol Marchal, Erik Jan Marinissen, Geert Van der Plas, Diederik Verkest, Eric Beyne. 403-410 [doi]
• Formal verification of distributed controllers using Time-Stamped Event Count AutomataMatthias Kauer, Sebastian Steinhorst, Dip Goswami, Reinhard Schneider 0001, Martin Lukasiewycz, Samarjit Chakraborty. 411-416 [doi]
• Reliability assessment of safety-relevant automotive systems in a model-based design flowSebastian Reiter, Michael Pressler, Alexander Viehl, Oliver Bringmann, Wolfgang Rosenstiel. 417-422 [doi]
• Sequential dependency and reliability analysis of embedded systemsHehua Zhang, Yu Jiang, Xiaoyu Song, William N. N. Hung, Ming Gu, Jiaguang Sun. 423-428 [doi]
• Processor and DRAM integration by TSV-based 3-D stacking for power-aware SOCsShin-Shiun Chen, Chun-Kai Hsu, Hsiu-Chuan Shih, Jen-Chieh Yeh, Cheng-Wen Wu. 429-434 [doi]
• A flexible fixed-outline floorplanning methodology for mixed-size modulesKai-Chung Chan, Chao-Jam Hsu, Jia-Ming Lin. 435-440 [doi]
• Optimizing routability in large-scale mixed-size placementJason Cong, Guojie Luo, Kalliopi Tsota, Bingjun Xiao. 441-446 [doi]
• Symmetrical buffered clock-tree synthesis with supply-voltage alignmentXin-Wei Shih, Tzu-Hsuan Hsu, Hsu-Chieh Lee, Yao-Wen Chang, Kai-Yuan Chao. 447-452 [doi]
• BonnCell: Automatic layout of leaf cellsStefan Hougardy, Tim Nieberg, Jan Schneider. 453-460 [doi]
• Register and thread structure optimization for GPUsYun Liang, Zheng Cui, Kyle Rupnow, Deming Chen. 461-466 [doi]
• Real-time partitioned scheduling on multi-core systems with local and global memoriesChe-Wei Chang, Jian-Jia Chen, Tei-Wei Kuo, Heiko Falk. 467-472 [doi]
• Dynamic thermal management for multi-core microprocessors considering transient thermal effectsZao Liu, Tailong Xu, Sheldon X.-D. Tan, Hai Wang. 473-478 [doi]
• BAMSE: A balanced mapping space exploration algorithm for GALS-based manycore platformsMohammad H. Foroozannejad, Brent Bohnenstiehl, Soheil Ghiasi. 479-484 [doi]
• Thermal simulator of 3D-IC with modeling of anisotropic TSV conductance and microchannel entrance effectsHanhua Qian, Hao Liang, Chip-Hong Chang, Wei Zhang, Hao Yu. 485-490 [doi]
• A novel cell placement algorithm for flexible TFT circuit with mechanical strain and temperature considerationJiun-Li Lin, Po-Hsun Wu, Tsung-Yi Ho. 491-496 [doi]
• Improving energy efficiency for energy harvesting embedded systemsYang Ge, Yukan Zhang, Qinru Qiu. 497-502 [doi]
• Modeling variability and irreproducibility of nanoelectronic resistive switches for circuit simulationArne Heittmann, Tobias G. Noll. 503-508 [doi]
• HS3DPG: Hierarchical simulation for 3D P/G networkShuai Tao, Xiaoming Chen, Yu Wang 0002, Yuchun Ma, Yiyu Shi, Hui Wang, Huazhong Yang. 509-514 [doi]
• Piecewise-polynomial associated transform macromodeling algorithm for fast nonlinear circuit simulationYang Zhang, Neric Fong, Ngai Wong. 515-520 [doi]
• An ultra-compact virtual source FET model for deeply-scaled devices: Parameter extraction and validation for standard cell libraries and digital circuitsLi Yu, Omar Mysore, Lan Wei, Luca Daniel, Dimitri A. Antoniadis, Ibrahim M. Elfadel, Duane S. Boning. 521-526 [doi]
• On potential design impacts of electromigration awarenessAndrew B. Kahng, Siddhartha Nath, Tajana Rosing. 527-532 [doi]
• Provably optimal test cube generation using quantified boolean formula solvingMatthias Sauer, Sven Reimer, Ilia Polian, Tobias Schubert, Bernd Becker. 533-539 [doi]
• Synthesizing multiple scan chains by cost-driven spectral orderingLouis Y.-Z. Lin, Christina C.-H. Liao, Charles H.-P. Wen. 540-545 [doi]
• A binding algorithm in high-level synthesis for path delay testabilityYuki Yoshikawa. 546-551 [doi]
• Full exploitation of process variation space for continuous delivery of optimal delay test qualityBaris Arslan, Alex Orailoglu. 552-557 [doi]
• SMYLE Project: Toward high-performance, low-power computing on manycore-processor SoCsKoji Inoue. 558-560 [doi]
• SMYLEref: A reference architecture for manycore-processor SoCsMasaaki Kondo, S. T. Nguyen, Tomoya Hirao, T. Soga, Hiroshi Sasaki, Koji Inoue. 561-564 [doi]
• SMYLE OpenCL: A programming framework for embedded many-core SoCsHiroyuki Tomiyama, Takuji Hieda, Naoki Nishiyama, Noriko Etani, Ittetsu Taniguchi. 565-567 [doi]
• Support tools for porting legacy applications to multicoreYuri Ardila, Natsuki Kawai, Takashi Nakamura, Yosuke Tamura. 568-573 [doi]
• Manycore processor for video mining applicationsYukoh Matsumoto, Hiroyuki Uchida, Michiya Hagimoto, Yasumori Hibi, Sunao Torii, Masamichi Izumida. 574-575 [doi]
• Native simulation of complex VLIW instruction sets using static binary translation and Hardware-Assisted VirtualizationMian Muhammad Hamayun, Frédéric Pétrot, Nicolas Fournel. 576-581 [doi]
• RExCache: Rapid exploration of unified last-level cacheSu Myat Min, Haris Javaid, Sri Parameswaran. 582-587 [doi]
• An efficient hybrid synchronization technique for scalable multi-core instruction set simulationsBo-Han Zeng, Ren-Song Tsay, Ting-Chi Wang. 588-593 [doi]
• Statistical analysis of BTI in the presence of process-induced voltage and temperature variationsFarshad Firouzi, Saman Kiamehr, Mehdi Baradaran Tahoori. 594-600 [doi]
• CLASS: Combined logic and architectural soft error sensitivity analysisMojtaba Ebrahimi, Liang Chen, Hossein Asadi, Mehdi Baradaran Tahoori. 601-607 [doi]
• Application specified soft error failure rate analysis using sequential equivalence checking techniquesTun Li, Dan Zhu, Sikun Li, Yang Guo. 608-613 [doi]
• An adaptive current-threshold determination for IDDQ testing based on Bayesian process parameter estimationMichihiro Shintani, Takashi Sato. 614-619 [doi]
• DARNS: A randomized multi-modulo RNS architecture for double-and-add in ECC to prevent power analysis side channel attacksJude Angelo Ambrose, Héctor Pettenghi, Leonel Sousa. 620-625 [doi]
• ScanPUF: Robust ultralow-overhead PUF using scan chainYu Zheng, Aswin Raghav Krishna, Swarup Bhunia. 626-631 [doi]
• An efficient compression scheme for checkpointing of FPGA-based digital mockupsTing-Shuo Chou, Tony Givargis, Chen Huang, Bailey Miller, Frank Vahid. 632-637 [doi]
• Maximizing return on investment of a grid-connected hybrid electrical energy storage systemDi Zhu, Yanzhi Wang, Siyu Yue, Qing Xie, Massoud Pedram, Naehyuck Chang. 638-643 [doi]
• Silicon photonics technology platform for embedded and integrated optical interconnect systemsPeter De Dobbelaere. 644-647 [doi]
• High-frequency circuit design for 25 Gb/s×4 optical transceiverNorio Chujo, Takashi Takemoto, Fumio Yuki, Hiroki Yamashita. 648-651 [doi]
• Design and application of highly integrated optical switches based on silicon photonicsShigeru Nakamura. 652-654 [doi]
• High performance PIN Ge photodetector and Si optical modulator with MOS junction for photonics-electronics convergence systemJunichi Fujikata, Masataka Noguchi, Makoto Miura, Masashi Takahashi, Shigeki Takahashi, Tsuyoshi Horikawa, Yutaka Urino, Takahiro Nakamura, Yasuhiko Arakawa. 655-656 [doi]
• Reevaluating the latency claims of 3D stacked memoriesDaniel W. Chang, Gyungsu Byun, Hoyoung Kim, Minwook Ahn, Soojung Ryu, Nam Sung Kim, Michael J. Schulte. 657-662 [doi]
• Heterogeneous memory management for 3D-DRAM and external DRAM with QoSLe-Nguyen Tran, Fadi J. Kurdahi, Ahmed M. Eltawil, Houman Homayoun. 663-668 [doi]
• Line sharing cache: Exploring cache capacity with frequent line value localityKeitarou Oka, Hiroshi Sasaki, Koji Inoue. 669-674 [doi]
• ShieldUS: A novel design of dynamic shielding for eliminating 3D TSV crosstalk coupling noiseYuan-Ying Chang, Yoshi Shih-Chieh Huang, Vijaykrishnan Narayanan, Chung-Ta King. 675-680 [doi]
• High-density integration of functional modules using monolithic 3D-IC technologyShreepad Panth, Kambiz Samadi, Yang Du, Sung Kyu Lim. 681-686 [doi]
• Block-level designs of die-to-wafer bonded 3D ICs and their design quality tradeoffsKrit Athikulwongse, Dae-Hyun Kim, Moongon Jung, Sung Kyu Lim. 687-692 [doi]
• Thermal-reliable 3D clock-tree synthesis considering nonlinear electrical-thermal-coupled TSV modelYang Shang, Chun Zhang, Hao Yu, Chuan Seng Tan, Xin Zhao, Sung Kyu Lim. 693-698 [doi]
• Stacking signal TSV for thermal dissipation in global routing for 3D ICPo-Yang Hsu, Hsien-Te Chen, TingTing Hwang. 699-704 [doi]
• VFCC: A verification framework of cache coherence using parallel simulationQiaoli Xiong, Jiangfang Yi, Tianbao Song, Zichao Xie, Dong Tong. 705-710 [doi]
• A computational model for SAT-based verification of hardware-dependent low-level embedded system softwareBernard Schmidt, Carlos Villarraga, Jörg Bormann, Dominik Stoffel, Markus Wedler, Wolfgang Kunz. 711-716 [doi]
• Reviving erroneous stability-based clock-gating using partial Max-SATBao Le, Dipanjan Sengupta, Andreas G. Veneris. 717-722 [doi]
• Simplification of C-RTL equivalent checking for fused multiply add unit using intermediate modelsBin Xue, Prosenjit Chatterjee, Sandeep K. Shukla. 723-728 [doi]
• Memory access reconstruction based on memory allocation mechanism for source-level simulation of embedded softwareKun Lu, Daniel Mueller-Gritschneder, Ulf Schlichtmann. 729-734 [doi]
• Shared cache aware task mapping for WCRT minimizationHuping Ding, Yun Liang, Tulika Mitra. 735-740 [doi]
• Scratchpad Memory aware task scheduling with minimum number of preemptions on a single processorQing Wan, Hui Wu, Jingling Xue. 741-748 [doi]
• An efficient scheduling algorithm for multiple charge migration tasks in hybrid electrical energy storage systemsQing Xie, Di Zhu, Yanzhi Wang, Massoud Pedram, Younghyun Kim, Naehyuck Chang. 749-754 [doi]
• Stable backward reachability correction for PLL verification with consideration of environmental noise induced jitterYang Song, Haipeng Fu, Hao Yu, Guoyong Shi. 755-760 [doi]
• Performance bound and yield analysis for analog circuits under process variationsXuexin Liu, Adolfo Adair Palma-Rodriguez, Santiago Rodriguez-Chavez, Sheldon X.-D. Tan, Esteban Tlelo-Cuautle, Yici Cai. 761-766 [doi]
• Local approximation improvement of trajectory piecewise linear macromodels through Chebyshev interpolating polynomialsMuhammad Umer Farooq, Likun Xia. 767-772 [doi]
• Range and bitmask analysis for hardware optimization in high-level synthesisMarcel Gort, Jason Helge Anderson. 773-779 [doi]
• A gradual scheduling framework for problem size reduction and cross basic block parallelism exploitation in high-level synthesisHongbin Zheng, Qingrui Liu, Junyi Li, Dihu Chen, Zixin Wang. 780-786 [doi]
• Implementing microprocessors from simplified descriptionsNikhil A. Patil, Derek Chiou. 787-793 [doi]
• Application-specific fault-tolerant architecture synthesis for digital microfluidic biochipsMirela Alistar, Paul Pop, Jan Madsen. 794-800 [doi]