Kiichi Niitsu, Naohiro Harigai, Daiki Hirabayashi, Daiki Oki, Masato Sakurai, Osamu Kobayashi, Takahiro J. Yamaguchi, Haruo Kobayashi. Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges. In 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013, Yokohama, Japan, January 22-25, 2013. pages 103-104, IEEE, 2013. [doi]
Abstract is missing.