Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Kiichi Niitsu, Naohiro Harigai, Daiki Hirabayashi, Daiki Oki, Masato Sakurai, Osamu Kobayashi, Takahiro J. Yamaguchi, Haruo Kobayashi. Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges. In 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013, Yokohama, Japan, January 22-25, 2013. pages 103-104, IEEE, 2013. [doi]

This author has not been identified. Look up 'Kiichi Niitsu' in GoogleThis author has not been identified. Look up 'Naohiro Harigai' in GoogleThis author has not been identified. Look up 'Daiki Hirabayashi' in GoogleThis author has not been identified. Look up 'Daiki Oki' in GoogleThis author has not been identified. Look up 'Masato Sakurai' in GoogleThis author has not been identified. Look up 'Osamu Kobayashi' in GoogleThis author has not been identified. Look up 'Takahiro J. Yamaguchi' in GoogleThis author has not been identified. Look up 'Haruo Kobayashi' in Google

runs on WebDSL