Processor and DRAM integration by TSV-based 3-D stacking for power-aware SOCs

Shin-Shiun Chen, Chun-Kai Hsu, Hsiu-Chuan Shih, Jen-Chieh Yeh, Cheng-Wen Wu. Processor and DRAM integration by TSV-based 3-D stacking for power-aware SOCs. In 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013, Yokohama, Japan, January 22-25, 2013. pages 429-434, IEEE, 2013. [doi]

Abstract

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