Shinji Miyano - researchr alias

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Viewing Publication 1 - 32 from 32

2014

13.4 A 7ns-access-time 25μW/MHz 128kb SRAM for low-power fast wake-up MCU in 65nm CMOS with 27fA/b retention currentToshikazu Fukuda, Koji Kohara, Toshiaki Dozaka, Yasuhisa Takeyama, Tsuyoshi Midorikawa, Kenji Hashimoto, Ichiro Wakiyama, Shinji Miyano, Takehiko Hojo. isscc 2014: 236-237 [doi]

2013

NBTI Reliability of PFETs under Post-Fabrication Self-Improvement Scheme for SRAMNurul Ezaila Alias, Anil Kumar, Takuya Saraya, Shinji Miyano, Toshiro Hiramoto. ieicet, 96-C(5):620-623, 2013. [doi]

Experimental Demonstration of Post-Fabrication Self-Improvement of SRAM Cell Stability by High-Voltage StressToshiro Hiramoto, Anil Kumar, Takuya Saraya, Shinji Miyano. ieicet, 96-C(6):759-765, 2013. [doi]

A 6T-SRAM With a Post-Process Electron Injection Scheme That Pinpoints and Simultaneously Repairs Disturb Fails for 57% Less Read Delay and 31% Less Read EnergyKousuke Miyaji, Toshikazu Suzuki, Shinji Miyano, Ken Takeuchi. jssc, 48(9):2239-2249, 2013. [doi]

Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line ChargesShinji Miyano, Shinichi Moriwaki, Yasue Yamamoto, Atsushi Kawasumi, Toshikazu Suzuki, Takayasu Sakurai, Hirofumi Shinohara. jssc, 48(4):924-931, 2013. [doi]

A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structureShusuke Yoshimoto, Shinji Miyano, Makoto Takamiya, Hirofumi Shinohara, Hiroshi Kawaguchi, Masahiko Yoshimoto. cicc 2013: 1-4 [doi]

A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation techniqueShusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto. aspdac 2013: 77-78 [doi]

2012

A 6T SRAM with a carrier-injection scheme to pinpoint and repair fails that achieves 57% faster read and 31% lower read energyKousuke Miyaji, Toshikazu Suzuki, Shinji Miyano, Ken Takeuchi. isscc 2012: 232-234 [doi]

Analysis of Operation Margin and Read Speed in 6T- and 8T-SRAM with Local Electron Injected Asymmetric Pass Gate TransistorKousuke Miyaji, Kentaro Honda, Shuhei Tanakamaru, Shinji Miyano, Ken Takeuchi. ieicet, 95-C(4):564-571, 2012. [doi]

Near Threshold Voltage Word-Line Voltage Injection Self-Convergence Scheme for Local Electron Injected Asymmetric Pass Gate Transistor 6T-SRAMKousuke Miyaji, Yasuhiro Shinozuka, Shinji Miyano, Ken Takeuchi. tcas, 59-I(8):1635-1643, 2012. [doi]

A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line chargesShinichi Moriwaki, Yasuhiro Yamamoto, Atsushi Kawasumi, T. Suzuki, Shinji Miyano, Takayasu Sakurai, Hirofumi Shinohara. vlsic 2012: 60-61 [doi]

A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reductionMasaharu Terada, Shusuke Yoshimoto, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto. isqed 2012: 489-492 [doi]

60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variationsYasue Yamamoto, Atsushi Kawasumi, Shinichi Moriwaki, Toshikazu Suzuki, Shinji Miyano, Hirofumi Shinohara. esscirc 2012: 317-320 [doi]

A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) schemeShusuke Yoshimoto, Masaharu Terada, Youhei Umeki, Shunsuke Okumura, Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto. islped 2012: 85-90 [doi]

A 40-nm 256-Kb Half-Select Resilient 8T SRAM with Sequential Writing TechniqueShusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto. ieiceee, 9(12):1023-1029, 2012. [doi]

A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation SchemeShusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto. ieicet, 95-C(4):572-578, 2012. [doi]

2011

Energy efficiency degradation caused by random variation in low-voltage SRAM and 26% energy reduction by Bitline Amplitude Limiting (BAL) schemeAtsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano. asscc 2011: 165-168 [doi]

Statistical VTH shift variation self-convergence scheme using near threshold VWL injection for local electron injected asymmetric pass gate transistor SRAMKousuke Miyaji, Yasuhiro Shinozuka, Shinji Miyano, Ken Takeuchi. cicc 2011: 1-4 [doi]

TH Mismatch Self-Repair in 6T-SRAM With Asymmetric Pass Gate Transistor Formed by Post-Process Local Electron InjectionKousuke Miyaji, Shuhei Tanakamaru, Kentaro Honda, Shinji Miyano, Ken Takeuchi. jssc, 46(9):2180-2188, 2011. [doi]

0.4V SRAM with bit line swing suppression charge share hierarchical bit line schemeShinichi Moriwaki, Atsushi Kawasumi, Toshikazu Suzuki, Takayasu Sakurai, Shinji Miyano. cicc 2011: 1-4 [doi]

2010

2008

2006

A 65nm low-power embedded DRAM with extended data-retention sleep modeTakeshi Nagai, Masaharu Wada, Hitoshi Iwai, Mariko Kaku, Atsushi Suzuki, Tomohisa Takai, Naoko Itoga, Takayuki Miyazaki, Hiroyuki Takenaka, Takehiko Hojo, Shinji Miyano. isscc 2006: 567-576 [doi]

2001

Interface socket design methodology to generate embedded DRAM macrosRyo Haga, Tetsuya Kaneko, Atsushi Nakayama, Shinji Miyano, Hiroyuki Takenaka, Kenji Numata, Hiroyuki Koinuma, Takehiko Hojo, Akikuni Sato, Toshiyuki Kouchi, Kenichiro Mimoto, Masaaki Tazawa, Tsutomu Ohkubo, Takanori Andou, Tetsuya Amano. cicc 2001: 537-540 [doi]

2000

Dynamically shift-switched dataline redundancy suitable for DRAM macro with wide data busToshimasa Namekawa, Shinji Miyano, Ryo Fukuda, Ryo Haga, Osamu Wada, Hironori Banba, Satoru Takeda, Kazuhiro Suda, Kenichiro Mimoto, Satoshi Yamaguchi, Tsutomu Ohkubo, Hiroshi Takato, Kenji Numata. jssc, 35(5):705-712, 2000. [doi]

1999

Universal Test Interface for Embedded-DRAM TestingShinji Miyano, Katsuhiko Sato, Kenji Numata. dt, 16(1):53-58, 1999. [doi]

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2014

2013

2012

2011

2010

2008

2006

2001

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1999

1998

1995

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