0.5-V, 150-MHz, bulk-CMOS SRAM with suspended bit-line read scheme - researchr publication

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Toshikazu Suzuki, Shinichi Moriwaki, Atsushi Kawasumi, Shinji Miyano, Hirofumi Shinohara. 0.5-V, 150-MHz, bulk-CMOS SRAM with suspended bit-line read scheme. In 36th European Solid-State Circuits Conference, ESSCIRC 2010, Sevilla, Spain, September 13-17, 2010. pages 354-357, IEEE, 2010. [doi]

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