A 65nm low-power embedded DRAM with extended data-retention sleep mode

Takeshi Nagai, Masaharu Wada, Hitoshi Iwai, Mariko Kaku, Atsushi Suzuki, Tomohisa Takai, Naoko Itoga, Takayuki Miyazaki, Hiroyuki Takenaka, Takehiko Hojo, Shinji Miyano. A 65nm low-power embedded DRAM with extended data-retention sleep mode. In 2006 IEEE International Solid State Circuits Conference, ISSCC 2006, Digest of Technical Papers, an Francisco, CA, USA, February 6-9, 2006. pages 567-576, IEEE, 2006. [doi]

Abstract

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