Abstract is missing.
- ForewordAjith Amerasekera, Makoto Nagata. 1-2 [doi]
- The evolution of next-generation data center networks for high capacity computingNick Ilyadis. 1-5 [doi]
- Technology innovations for smart citiesAkira Maeda. 6-9 [doi]
- Components for generating and phase locking 390-GHz signal in 45-nm CMOSDongha Shim, Dimitrios Koukis, Daniel J. Arenas, David B. Tanner, Eunyoung Seok, Joe E. Brewer, Kenneth K. O. 10-11 [doi]
- A 160-GHz receiver-based phase-locked loop in 65 nm CMOS technologyWei-Zen Chen, Tai-You Lu, Yan-Ting Wang, Jhong-Ting Jian, Yi-Hung Yang, Guo-Wei Huang, Wen-De Liu, Chih-Hua Hsiao, Shu-Yu Lin, Jung Yen Liao. 12-13 [doi]
- A 32.4 ppm/°C 3.2-1.6V self-chopped relaxation oscillator with adaptive supply generationKeng-Jan Hsiao. 14-15 [doi]
- A 280nW, 100kHz, 1-cycle start-up time, on-chip CMOS relaxation oscillator employing a feedforward period control schemeTakashi Tokairin, Koichi Nose, Koichi Takeda, Koichiro Noguchi, Tadashi Maeda, Kazuyoshi Kawai, Masayuki Mizuno. 16-17 [doi]
- Circuit techniques to overcome Class-D audio amplifier limitations in mobile devicesXicheng Jiang, Jungwoo Song, Minsheng Wang, Jianlong Chen, Sasi Kumar Arunachalam, Todd L. Brooks. 18-19 [doi]
- A 5.2mW, 0.0016% THD up to 20kHz, ground-referenced audio decoder with PSRR-enhanced class-AB 16Ω headphone amplifiersShon-Hang Wen, Cheng-Chung Yang. 20-21 [doi]
- A sub-1V 3.9µW bandgap reference with a 3σ inaccuracy of ±0.34% from -50°C to +150°C using piecewise-linear-current curvature compensationShinya Sano, Yasuhiko Takahashi, Masashi Horiguchi, Moriyoshi Ota. 22-23 [doi]
- A 1.2V 8.3nJ energy-efficient CMOS humidity sensor for RFID applicationsZhichao Tan, Youngcheol Chae, Roel Daamen, Aurelie Humbert, Youri V. Ponomarev, Michiel A. P. Pertijs. 24-25 [doi]
- A 6b 3GS/s 11mW fully dynamic flash ADC in 40nm CMOS with reduced number of comparatorsYun-Shiang Shu. 26-27 [doi]
- An event-driven, alias-free ADC with signal-dependent resolutionColin Weltin-Wu, Yannis P. Tsividis. 28-29 [doi]
- A 10-bit 1-GHz 33-mW CMOS ADCBibhu Datta Sahoo, Behzad Razavi. 30-31 [doi]
- A 61.5dB SNDR pipelined ADC using simple highly-scalable ring amplifiersBenjamin P. Hershberg, Skyler Weaver, Kazuki Sobue, Seiji Takeuchi, Koichi Hamashita, Un-Ku Moon. 32-33 [doi]
- A 440pJ/bit 1Mb/s 2.4GHz multi-channel FBAR-based TX and an integrated pulse-shaping PAArun Paidimarri, Phillip M. Nadeau, Patrick P. Mercier, Anantha P. Chandrakasan. 34-35 [doi]
- An 8-PPM, 45 pJ/bit UWB transmitter with reduced number of PA elementsVahid Majidzadeh, Alexandre Schmid, Yusuf Leblebici, Jan M. Rabaey. 36-37 [doi]
- An all 0.5V, 1Mbps, 315MHz OOK transceiver with 38-µW career-frequency-free intermittent sampling receiver and 52-µW class-F transmitter in 40-nm CMOSAkira Saito, Kentaro Honda, Yun Fei Zheng, Shunta Iguchi, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya. 38-39 [doi]
- A 2.4GHz hybrid PPF based BFSK receiver with ±180ppm frequency offset tolerance for wireless sensor networksRonghua Ni, Kartikeya Mayaram, Terri S. Fiez. 40-41 [doi]
- A 0.13µm 8Mb logic based CuxSiyO resistive memory with self-adaptive yield enhancement and operation power reductionX. Y. Xue, W. X. Jian, J.-G. Yang, F. J. Xiao, G. Chen, X. L. Xu, Y. F. Xie, Y. Y. Lin, R. Huang, Q. T. Zhou, J. G. Wu. 42-43 [doi]
- 2 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architectureShoun Matsunaga, Sadahiko Miura, Hiroaki Honjou, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu. 44-45 [doi]
- 1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off timesTakashi Ohsawa, Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Keiichi Tokutome, S. Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh. 46-47 [doi]
- A 260 GHz fully integrated CMOS transceiver for wireless chip-to-chip communicationJung-Dong Park, Shinwon Kang, Siva V. Thyagarajan, Elad Alon, Ali M. Niknejad. 48-49 [doi]
- 135 GHz 98 mW 10 Gbps ASK transmitter and receiver chipset in 40 nm CMOSNaoko Ono, Mizuki Motoyoshi, Kyoya Takano, Kosuke Katayama, Ryuichi Fujimoto, Minoru Fujishima. 50-51 [doi]
- A 21.5mW 10+Gb/s mm-Wave phased-array transmitter in 65nm CMOSLingkai Kong, Elad Alon. 52-53 [doi]
- A UWB IR timed-array radar using time-shifted direct-sampling architectureChang-Ming Lai, Kai-Wen Tan, Liu-Yuan Yu, Yen-Ju Chen, Jun-Wei Huang, Shr-Chau Lai, Feng-Hsu Chung, Chia-Fung Yen, Jen-Ming Wu, Po-Chiun Huang, Keh-Jeng Chang, Shi-Yu Huang, Ta-Shun Chu. 54-55 [doi]
- A 94GHz mm-wave to baseband pulsed-radar for imaging and gesture recognitionAmin Arbabian, Shinwon Kang, Steven Callender, Jun-Chau Chien, Bagher Afshar, Ali Niknejad. 56-57 [doi]
- A 0.41µA standby leakage 32Kb embedded SRAM with Low-Voltage resume-standby utilizing all digital current comparator in 28nm HKMG CMOSNoriaki Maeda, Shigenobu Komatsu, Masao Morimoto, Yasuhisa Shimazaki. 58-59 [doi]
- A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line chargesShinichi Moriwaki, Yasuhiro Yamamoto, Atsushi Kawasumi, T. Suzuki, Shinji Miyano, Takayasu Sakurai, Hirofumi Shinohara. 60-61 [doi]
- A SRAM cell array with adaptive leakage reduction scheme for data retention in 28nm high-k metal-gate CMOSPeter Kuoyuan Hsu, Yukit Tang, Derek Tao, Ming-Chieh Huang, Min-Jer Wang, C. H. Wu, Quincy Lee. 62-63 [doi]
- 2RA) circuitry achieving 3x reduction on speed variation for single ended arraysRobin Lee, Jung-Ping Yang, Chia-En Huang, Chih-Chieh Chiu, Wei-Shuo Kao, Hong-Chen Cheng, Hong-Jen Liao, Jonathan Chang. 64-65 [doi]
- A 0.6V 2.9µW mixed-signal front-end for ECG monitoringMarcus Yip, Jose L. Bohorquez, Anantha P. Chandrakasan. 66-67 [doi]
- A 700µW 8-channel EEG/contact-impedance acquisition system for dry-electrodesSrinjoy Mitra, Jiawei Xu, Akinori Matsumoto, Kofi A. A. Makinwa, Chris Van Hoof, Refet Firat Yazicioglu. 68-69 [doi]
- A wirelessly powered log-based closed-loop deep brain stimulation SoC with two-way wireless telemetry for treatment of neurological disordersHyo-Gyuem Rhew, Jaehun Jeong, Jeffrey A. Fredenburg, Sunjay Dodani, Parag G. Patil, Michael P. Flynn. 70-71 [doi]
- 2) wireless neural sensorDaniel J. Yeager, William Biederman, Nathan Narevsky, Elad Alon, Jan M. Rabaey. 72-73 [doi]
- A -70dBm-sensitivity 522Mbps 0.19nJ/bit-TX 0.43nJ/bit-RX transceiver for TransferJet™ SoC in 65nm CMOSDaisuke Miyashita, Kenichi Agawa, Hirotsugu Kajihara, Kenichi Sami, Masaomi Iwanaga, Yosuke Ogasawara, Tomohiko Ito, Daisuke Kurose, Naotaka Koide, Toru Hashimoto, Hiroki Sakurai, Takafumi Yamaji, Takashi Kurihara, Kazumi Sato, Ichiro Seto, Hiroshi Yoshida, Ryuichi Fujimoto, Yasuo Unekawa. 74-75 [doi]
- A 2.4GHz WLAN transceiver with fully-integrated highly-linear 1.8V 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOSYulin Tan, Jon Duster, Chang-Tsung Fu, Erkan Alpman, Ajay Balankutty, Chun C. Lee, Ashoke Ravi, Stefano Pellerano, Kailash Chandrashekar, Hyung Seok Kim, Brent R. Carlton, Ssatoshi Suzuki, M. Shafi, Yorgos Palaskas, Hasnain Lakdawala. 76-77 [doi]
- A +30.5 dBm CMOS Doherty power amplifier with reliability enhancement techniqueKohei Onizuka, Shigehito Saigusa, Shoji Otaka. 78-79 [doi]
- A harmonic-rejecting CMOS LNA for broadband radiosJoung Won Park, Behzad Razavi. 80-81 [doi]
- A 13.5mA sub-2.5dB NF multi-band receiverMohyee Mikhemar, Ahmad Mirzaei, Amir Hadji-Abdolhamid, Janice Chiu, Hooman Darabi. 82-83 [doi]
- A 2.8GS/s 44.6mW time-interleaved ADC achieving 50.9dB SNDR and 3dB effective resolution bandwidth of 1.5GHz in 65nm CMOSDusan Stepanovic, Borivoje Nikolic. 84-85 [doi]
- A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structureChi-Hang Chan, Yan Zhu 0001, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins. 86-87 [doi]
- A 4.5-mW 8-b 750-MS/s 2-b/step asynchronous subranged SAR ADC in 28-nm CMOS technologyYuan-Ching Lien. 88-89 [doi]
- A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADCYan Zhu 0001, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins. 90-91 [doi]
- A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOSHung-Yen Tai, Hung-Wei Chen, Hsin-Shu Chen. 92-93 [doi]
- A 22nm dynamically adaptive clock distribution for voltage droop toleranceKeith A. Bowman, Carlos Tokunaga, Tanay Karnik, Vivek K. De, Jim Tschanz. 94-95 [doi]
- Voltage droop reduction using throttling controlled by timing margin feedbackMichael S. Floyd, Alan J. Drake, Robert W. Berry, Harold Chase, Richard L. Willaman, Jarom Pena. 96-97 [doi]
- An on-die all-digital delay measurement circuit with 250fs accuracyMozhgan Mansuri, Bryan Casper, Frank O'Mahony. 98-99 [doi]
- A 47% access time reduction with a worst-case timing-generation scheme utilizing a statistical method for ultra low voltage SRAMsAtsushi Kawasumi, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe. 100-101 [doi]
- A 3.1mW/Gbps 30Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32nm CMOSThomas Toifl, Michael Ruegg, Rajesh Inti, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Peter Buchmann, Pier Andrea Francese, Thomas Morf. 102-103 [doi]
- A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOSJafar Savoj, Kenny C.-H. Hsieh, Parag Upadhyaya, Fu-Tai An, Ade Bekele, Stanley Chen, Xuewen Jiang, Kang Wei Lai, Chi Fung Poon, Aman Sewani, Didem Turker, Karthik Venna, Zhaoyin Daniel Wu, Bruce Xu, Elad Alon, Ken Chang. 104-105 [doi]
- A 25-Gb/s 2.2-W optical transceiver using an analog FE tolerant to power supply noise and redundant data format conversion in 65-nm CMOSTakashi Takemoto, Hiroki Yamashita, Takehito Kamimura, Fumio Yuki, Noboru Masuda, Hidehiro Toyoda, Norio Chujo, Kenji Kogo, Yong Lee, Shinji Tsuji, Shinji Nishimura. 106-107 [doi]
- A 100+ meter 12Gb/s/lane copper cable link based on clock-forwardingTamer A. Ali, Won-Ho Park, Preeti Mulage, E.-Hung Chen, Ron Ho, Chih-Kong Ken Yang. 108-109 [doi]
- Isolated Preset Architecture for a 32nm SOI embedded DRAM macroJohn Barth, Don Plass, Adis Vehabovic, Rajiv V. Joshi, Rouwaida Kanj, Steven Burns, Todd Weaver. 110-111 [doi]
- A 260mV L-shaped 7T SRAM with bit-line (BL) Swing expansion schemes based on boosted BL, asymmetric-VTH read-port, and offset cell VDD biasing techniquesMing-Pin Chen, Lai-Fu Chen, Meng-Fan Chang, Shu-Meng Yang, Yao-Jen Kuo, Jui-Jen Wu, Mon-Shu Ho, Hsiu-Yun Su, Yuan-Hua Chu, Wen-Chin Wu, Tzu-Yi Yang, Hiroyuki Yamauchi. 112-113 [doi]
- 2 38-mW 1.5-Gb/s LDPC decoder enabled by refresh-free embedded DRAMYoun Sung Park, David Blaauw, Dennis Sylvester, Zhengya Zhang. 114-115 [doi]
- 1Gsearch/sec Ternary Content Addressable Memory compiler with silicon-aware Early-Predict Late-Correct single-ended sensingIgor Arsovski, Travis Hebig, Daniel Dobson, Reid Wistort. 116-117 [doi]
- A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOSSteven Hsu, Amit Agarwal, Mark Anders, Himanshu Kaul, Sanu Mathew, Farhana Sheikh, Ram Krishnamurthy, Shekhar Borkar. 118-119 [doi]
- High-resolution sensing sheet for structural-health monitoring via scalable interfacing of flexible electronics with high-performance ICsYingzhe Hu, Warren Rieutort-Louis, Josue Sanz-Robinson, Katherine Song, James C. Sturm, Sigurd Wagner, Naveen Verma. 120-121 [doi]
- Nanostructured CMOS wireless ultra-wideband label-free DNA analysis SoCHamed Mazhab-Jafari, Leyla Soleymani, Karim Abdelhalim, Edward H. Sargent, Shana O. Kelley, Roman Genov. 122-123 [doi]
- A fully integrated hepatitis B virus DNA detection SoC based on monolithic polysilicon nanowire CMOS processChe-Wei Huang, Yu-Jie Huang, Pei-Wen Yen, Hsiao-Ting Hsueh, Chia-Yi Lin, Min-Cheng Chen, ChiaHua Ho, Fu-Liang Yang, Hann-Huei Tsai, Hsin-Hao Liao, Ying-Zong Juang, Chorng-Kuang Wang, Chih-Ting Lin, Shey-Shi Lu. 124-125 [doi]
- A fully-electronic charge-based DNA sequencing CMOS biochipArun Manickam, Rituraj Singh, Nicholas Wood, Bingling Li, Andrew D. Ellington, Arjang Hassibi. 126-127 [doi]
- An 88dB SNR, 30µm pixel pitch Infra-Red image sensor with a 2-step 16 bit A/D conversionArnaud Peizerat, Jean-Pierre Rostaing, Noureddine Zitouni, Nicolas Baier, Fabrice Guellec, Remi Jalby, Michaël Tchagaspanian. 128-129 [doi]
- A logic-compatible embedded flash memory featuring a multi-story high voltage switch and a selective refresh schemeSeung-hwan Song, Ki Chul Chun, Chris H. Kim. 130-131 [doi]
- A new 3-bit programming algorithm using SLC-to-TLC migration for 8MB/s high performance TLC NAND flash memorySeung-Hwan Shin, Dong-Kyo Shim, JaeYong Jeong, Ohsuk Kwon, Sangyong Yoon, Myung-Hoon Choi, Tae-young Kim, Hyun Wook Park, Hyun-Jun Yoon, Youngsun Song, Yoon-Hee Choi, Sang-Won Shim, Yang-Lo Ahn, Ki Tae Park, Jin-Man Han, Kyehyun Kyung, Young-Hyun Jun. 132-133 [doi]
- x11 performance increase, x6.9 endurance enhancement, 93% energy reduction of 3D TSV-integrated hybrid ReRAM/MLC NAND SSDs by data fragmentation suppressionHiroki Fujii, Kousuke Miyaji, Koh Johguchi, Kazuhide Higuchi, Chao Sun, Ken Takeuchi. 134-135 [doi]
- Adaptive multi-pulse program scheme based on tunneling speed classification for next generation multi-bit/cell NAND FLASHYong-Sung Cho, Il Han Park, Sang Young Yoon, Nam Hee Lee, Sang-Hyun Joo, Ki-Whan Song, Kihwan Choi, Jin-Man Han, Kyehyun Kyung, Young-Hyun Jun. 136-137 [doi]
- A 25-Gb/s 5-mWCMOS CDR/deserializerJun Won Jung, Behzad Razavi. 138-139 [doi]
- 4×12 Gb/s 0.96 pJ/b/lane analog-IIR crosstalk cancellation and signal reutilization receiver for single-ended I/Os in 65 nm CMOSTaehyoun Oh, Ramesh Harjani. 140-141 [doi]
- A clock jitter reduction circuit using gated phase blending between self-delayed clock edgesKiichi Niitsu, Naohiro Harigai, Daiki Hirabayashi, Daiki Oki, Masato Sakurai, Osamu Kobayashi, Takahiro J. Yamaguchi, Haruo Kobayashi. 142-143 [doi]
- 1.22mW/Gb/s 9.6Gb/s data jitter mixing forwarded-clock receiver robust against power noise with 1.92ns latency mismatch between data and clock in 65nm CMOSSang-Hye Chung, Lee-Sup Kim. 144-145 [doi]
- Dynamic intrinsic chip ID using 32nm high-K/metal gate SOI embedded DRAMDaniel Fainstein, Sami Rosenblatt, Alberto Cestero, Norman Robson, Toshiaki Kirihata, Subramanian S. Iyer. 146-147 [doi]
- A fully-digital phase-locked low dropout regulator in 32nm CMOSArijit Raychowdhury, Dinesh Somasekhar, James Tschanz, Vivek De. 148-149 [doi]
- A low power many-core SoC with two 32-core clusters connected by tree based NoC for multimedia applicationsHui Xu, Jun Tanabe, Hiroyuki Usui, Soichiro Hosoda, Toru Sano, Kazumasa Yamamoto, Takeshi Kodaka, Nobuhiro Nonogaki, Nau Ozaki, Takashi Miyamori. 150-151 [doi]
- A 69mW 140-meter/60fps and 60-meter/300fps intelligent vision SoC for versatile automotive applicationsYi-Min Tsai, Tien-Ju Yang, Chih-Chung Tsai, Keng-Yen Huang, Liang-Gee Chen. 152-153 [doi]
- A 4320p 60fps H.264/AVC intra-frame encoder chip with 1.41Gbins/s CABACDajiang Zhou, Gang He, Wei Fei, Zhixiang Chen, Jinjia Zhou, Satoshi Goto. 154-155 [doi]
- A sub-100µW multi-functional cardiac signal processor for mobile healthcare applicationsShu-Yu Hsu, Yingchieh Ho, Yuhwai Tseng, Ting-You Lin, Po-Yao Chang, Jen-Wei Lee, Ju-Hung Hsiao, Siou-Ming Chuang, Tze-Zheng Yang, Po-Chun Liu, Ten-Fang Yang, Ray-Jade Chen, Chauchin Su, Chen-Yi Lee. 156-157 [doi]
- A 0.25V 460nW asynchronous neural signal processor with inherent leakage suppressionTsung-Te Liu, Jan M. Rabaey. 158-159 [doi]
- A 10 MHz BW 50 fJ/conv. continuous time ΔΣ modulator with high-order single opamp integrator using optimization-based design methodKazuo Matsukawa, Koji Obata, Yosuke Mitani, Shiro Dosho. 160-161 [doi]
- A 5MHz BW 70.7dB SNDR noise-shaped two-step quantizer based ΔΣ ADCTaehwan Oh, Nima Maghari, Un-Ku Moon. 162-163 [doi]
- An 85dB SFDR 67dB SNDR 8OSR 240MS/s ΔΣ ADC with nonlinear memory error calibrationSeung-Chul Lee, Brian Elies, Yun Chiu. 164-165 [doi]
- A reconfigurable mostly-digital ΔΣ ADC with a worst-case FOM of 160dBGerry Taylor, Ian Galton. 166-167 [doi]
- A 71dB dynamic range third-order ΔΣ TDC using charge-pumpManideep Gande, Nima Maghari, Taehwan Oh, Un-Ku Moon. 168-169 [doi]
- A shorted global clock design for multi-GHz 3D stacked chipsLiang-Teck Pang, Phillip J. Restle, Matthew R. Wordeman, Joel A. Silberman, Robert L. Franch, Gary W. Maier. 170-171 [doi]
- A 3-stage Pseudo Single-phase Flip-flop familyHamid Partovi, Alfred Yeung, Luca Ravezzi, Mark Horowitz. 172-173 [doi]
- A standard cell compatible bidirectional repeater with thyristor assistSudhir Satpathy, Dennis Sylvester, David Blaauw. 174-175 [doi]
- An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOSMark A. Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander Rylyakov, Benjamin D. Parker, Aydin Babakhani, Soner Yaldiz, Bodhisatwa Sadhu, Alberto Valdes-Garcia, José A. Tierno, Daniel J. Friedman. 176-177 [doi]
- A 50nA quiescent current asynchronous digital-LDO with PLL-modulated fast-DVS power management in 40nm CMOS for 5.6 times MIPS performanceYu-Huei Lee, Shen-Yu Peng, Alex Chun-Hsien Wu, Chao-Chang Chiu, Yao-Yi Yang, Ming-Hsin Huang, Ke-Horng Chen, Ying-Hsi Lin, Shih-Wei Wang, Ching-Yuan Yeh, Chen-Chih Huang, Chao-Cheng Lee. 178-179 [doi]
- High area-efficient DC-DC converter using Time-Mode Miller Compensation (TMMC)Sung-Wan Hong, Tae-Hwang Kong, Seungchul Jung, Sungwoo Lee, Se-Won Wang, Jong-Pil Im, Gyu-Hyeong Cho. 180-181 [doi]
- A 900mA 93% efficient 50µA quiescent current fixed frequency hysteretic buck converter using a highly digital hybrid voltage- and current-mode controlQadeer Khan, Amr Elshazly, Sachin Rao, Rajesh Inti, Pavan Kumar Hanumolu. 182-183 [doi]
- A 198-ns/V VO-hopping reconfigurable RGB LED driver with automatic ΔVO detection and quasi-constant-frequency predictive peak current controlYi Zhang, Hai Chen, Dongsheng Ma. 184-185 [doi]
- Design of a 2.5-GHz, 3-ps jitter, 8-locking-cycle, all-digital delay-locked loop with cycle-by-cycle phase adjustmentChun-Yuan Cheng, Jinn-Shyan Wang, Cheng-Tai Yeh, Jenn-Shyan Sheu. 186-187 [doi]
- A 1.5GHz 1.35mW -112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivityAmr Elshazly, Rajesh Inti, Mrunmay Talegaonkar, Pavan Kumar Hanumolu. 188-189 [doi]
- 2 second-order all-digital TDC with low-jitter frequency shift oscillators and dynamic flipflopsToshihiro Konishi, Keisuke Okuno, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi. 190-191 [doi]
- A 7b, 3.75ps resolution two-step time-to-digital converter in 65nm CMOS using pulse-train time amplifierKwangSeok Kim, Young-Hwa Kim, Wonsik Yu, SeongHwan Cho. 192-193 [doi]
- A 0.45-V input on-chip gate boosted (OGB) buck converter in 40-nm CMOS with more than 90% efficiency in load range from 2µW to 50µWXin Zhang, Po-Hung Chen, Yoshikatsu Ryu, Koichi Ishida, Yasuyuki Okuma, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya. 194-195 [doi]
- A fully electrical startup batteryless boost converter with 50mV input voltage for thermoelectric energy harvestingHao-Yen Tang, Po-Shuan Weng, Po-Chih Ku, Liang-Hung Lu. 196-197 [doi]
- Integrated all-silicon thin-film power electronics on flexible sheets for ubiquitous wireless charging stations based on solar-energy harvestingLiechao Huang, Warren Rieutort-Louis, Yingzhe Hu, Josue Sanz-Robinson, Sigurd Wagner, James C. Sturm, Naveen Verma. 198-199 [doi]
- A 2.98nW bandgap voltage reference using a self-tuning low leakage sample and holdYen-Po Chen, Matthew Fojtik, David Blaauw, Dennis Sylvester. 200-201 [doi]
- A 635pW battery voltage supervisory circuit for miniature sensor nodesInhee Lee, Suyoung Bang, Yoonmyung Lee, Yejoong Kim, Gyouho Kim, Dennis Sylvester, David Blaauw. 202-203 [doi]