Phillip J. Restle - researchr alias

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Viewing Publication 1 - 22 from 22

2025

8.1 Dynamic Guard-Band Features of the IBM zNext SystemTobias Webel, Phillip J. Restle, Ramon Bertran, Alper Buyuktosunoglu, Sean M. Carey, Alejandro Cook, Karl Anderson, Michael Romain, Thomas Strach, Pradeep Bhadravati Parashurama, Aishwarya Tadkase, Rahman Abber Tahir, Luke Jenkins, Kevin Low, Eberhard Engler. isscc 2025: 1-3 [doi]

2023

Deterministic Frequency and Voltage Enhancements on the POWER10 ProcessorBrian T. Vanderpool, Phillip J. Restle, Eric Fluhr, Gregory S. Still, Francesco A. Campisano, Ian Charmichael, Eric Marz, Rahul Batra, Richard L. Willaman. jssc, 58(1):102-110, 2023. [doi]

2022

TM ProcessorBrian T. Vanderpool, Phillip J. Restle, Eric J. Fluhr, Gregory S. Still, Frank Campisano, Ian Carmichael, Eric Marz, Rahul Batra, Richard L. Willaman. isscc 2022: 1-3 [doi]

2019

2018

Droop mitigation using critical-path sensors and an on-chip distributed power supply estimation engine in the z14™ enterprise processorChristos Vezyrtzis, Thomas Strach, Pierce I-Jen Chuang, Preetham Lobo, Richard F. Rizzolo, Tobias Webel, Pawel Owczarczyk, Alper Buyuktosunoglu, Ramon Bertran, David T. Hui, Susan M. Eickhoff, Michael S. Floyd, Gerard Salem, Sean M. Carey, Stelios G. Tsapepas, Phillip J. Restle. isscc 2018: 300-302 [doi]

2017

26.5 Adaptive clocking in the POWER9™ processor for voltage droop protectionMichael S. Floyd, Phillip J. Restle, Michael A. Sperling, Pawel Owczarczyk, Eric J. Fluhr, Joshua Friedrich, Paul Muench, Timothy Diemoz, Pierce Chuang, Christos Vezyrtzis. isscc 2017: 444-445 [doi]

2015

2012

A shorted global clock design for multi-GHz 3D stacked chipsLiang-Teck Pang, Phillip J. Restle, Matthew R. Wordeman, Joel A. Silberman, Robert L. Franch, Gary W. Maier. vlsic 2012: 170-171 [doi]

Subtractive Router for Tree-Driven-Grid ClocksHaifeng Qian, Phillip J. Restle, Joseph N. Kozhaya, Clifford L. Gunion. tcad, 31(6):868-877, 2012. [doi]

2011

2009

A Resonant Global Clock Distribution for the Cell Broadband Engine ProcessorSteven C. Chan, Phillip J. Restle, Thomas J. Bucelot, John S. Liberty, Stephen Weitzel, John M. Keaty, Brian K. Flachs, Richard Volant, Peter Kapusta, Jeffrey S. Zimmerman. jssc, 44(1):64-72, 2009. [doi]

2007

2006

Distributed Differential Oscillators for Global Clock NetworksSteven C. Chan, Kenneth L. Shepard, Phillip J. Restle. jssc, 41(9):2083-2094, 2006. [doi]

A 5GHz Duty-Cycle Correcting Clock Distribution Network for the POWER6 MicroprocessorM. G. R. Thomson, Phillip J. Restle, Norman K. James. isscc 2006: 1522-1529 [doi]

2005

Uniform-phase uniform-amplitude resonant-load global clock distributionsSteven C. Chan, Kenneth L. Shepard, Phillip J. Restle. jssc, 40(1):102-109, 2005. [doi]

2003

Loop-based interconnect modeling and optimization approach for multigigahertz clock network designXuejue Huang, Phillip J. Restle, Thomas J. Bucelot, Yu Cao, Tsu-Jae King 0001, Chenming Hu. jssc, 38(3):457-463, 2003. [doi]

2002

Loop-based interconnect modeling and optimization approach for multi-GHz clock network designXuejue Huang, Phillip J. Restle, Thomas J. Bucelot, Yu Cao, Tsu-Jae King 0001. cicc 2002: 19-22 [doi]

2001

A clock distribution network for microprocessorsPhillip J. Restle, Timothy G. McNamara, David A. Webber, Peter J. Camporese, Kwok F. Eng, Keith A. Jenkins, David H. Allen, Michael J. Rohn, Michael P. Quaranta, David W. Boerstler, Charles J. Alpert, Craig A. Carter, Roger N. Bailey, John G. Petrovick, Byron L. Krauter, Bradley D. McCredie. jssc, 36(5):792-799, 2001. [doi]

1998

Measurement and modeling of on-chip transmission line effects in a 400 MHz microprocessorPhillip J. Restle, Keith A. Jenkins, Alina Deutsch, Peter W. Cook. jssc, 33(4):662-665, 1998. [doi]

1997

1989

A 3.5 ns/77 K and 6.2 ns/300 K 64 K CMOS RAM with ECL interfacesTerry I. Chappell, Stanley E. Schuster, Barbara A. Chappell, James W. Allan, Jack Y.-C. Sun, Stephen P. Klepner, Robert L. Franch, Paul F. Greier, Phillip J. Restle. jssc, 24(4):859-868, August 1989. [doi]

1988

Fast CMOS ECL receivers with 100-mV worst-case sensitivityBarbara A. Chappell, Terry I. Chappell, Stanley E. Schuster, Hermann M. Segmuller, James W. Allan, Robert L. Franch, Phillip J. Restle. jssc, 23(1):59-67, February 1988. [doi]

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