Stanley E. Schuster - researchr alias

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Viewing Publication 1 - 4 from 4

1992

On-chip test circuitry for a 2-ns cycle, 512-kb CMOS ECL SRAMStanley E. Schuster, Terry I. Chappell, Barbara A. Chappell, Robert L. Franch. jssc, 27(7):1073-1079, July 1992. [doi]

1991

A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architectureTerry I. Chappell, Barbara A. Chappell, Stanley E. Schuster, James W. Allan, Stephen P. Klepner, Rajiv V. Joshi, Robert L. Franch. jssc, 26(11):1577-1585, November 1991. [doi]

1989

A 3.5 ns/77 K and 6.2 ns/300 K 64 K CMOS RAM with ECL interfacesTerry I. Chappell, Stanley E. Schuster, Barbara A. Chappell, James W. Allan, Jack Y.-C. Sun, Stephen P. Klepner, Robert L. Franch, Paul F. Greier, Phillip J. Restle. jssc, 24(4):859-868, August 1989. [doi]

1988

Fast CMOS ECL receivers with 100-mV worst-case sensitivityBarbara A. Chappell, Terry I. Chappell, Stanley E. Schuster, Hermann M. Segmuller, James W. Allan, Robert L. Franch, Phillip J. Restle. jssc, 23(1):59-67, February 1988. [doi]

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