Abstract is missing.
- A CMOS Molecular Electronics Chip for Single-Molecule BiosensingDrew A. Hall, Nagaraj Ananthapad Manabhan, Chulmin Choi, Le Zheng, Paul P. Pan, Carl W. Fuller, Pius P. Padayatti, Calvin Gardner, Daniel Gebhardt, Zsolt Majzik, Prem Sinha, Paul W. Mola, Barry Merriman. 1-3 [doi]
- A 96.2nJ/class Neural Signal Processor with Adaptable Intelligence for Seizure PredictionYi-Yen Hsieh, Yu-Cheng Lin, Chia-Hsiang Yang. 1-3 [doi]
- A WiFi and Bluetooth Backscattering Combo Chip Featuring Beam Steering via a Fully-Reflective Phased-Controlled Multi-Antenna Termination Technique Enabling Operation Over 56 MetersShihkai Kuo, Manideep Dunna, Dinesh Bharadia, Patrick P. Mercier. 1-3 [doi]
- nd-Generation 7nm x86-64 Microprocessor CoreThomas Burd, Wilson Li, James Pistole, Srividhya Venkataraman, Michael McCabe, Timothy Johnson, James Vinh, Thomas Yiu, Mark Wasio, Hon-Hin Wong, Daryl Lieu, Jonathan White, Benjamin Munger, Joshua Lindner, Javin Olson, Steven Bakke, Jeshuah Sniderman, Carson Henrion, Russell Schreiber, Eric Busta, Brett Johnson, Tim Jackson, Aron Miller, Ryan Miller, Matthew Pickett, Aaron Horiuchi, Josef Dvorak, Sabeesh Balagangadharan, Sajeesh Ammikkallingal, Pankaj Kumar. 1-3 [doi]
- A Supply-Noise-Induced Jitter-Cancelling Clock Distribution Network for LPDDR5 Mobile DRAM featuring a 2nd-order Adaptive FilterYeonwook Jung, Seongseop Lee, Hyojun Kim, SeongHwan Cho. 1-3 [doi]
- 2 Single-Ended DECS TRX with CDR-less Self-Slicing/Auto-Deserialization to Improve Tolerance on Duty Cycle Error and RX Supply Noise for DCC/CDR-less Short-Reach Memory InterfacesJaeyoung Seo, Sooeun Lee, Myungguk Lee, Changjae Moon, Byungsub Kim. 1-3 [doi]
- A HD 31fps 7×7-View Light-Field Factorization Processor for Dual-Layer 3D Factored DisplayLi-Qun Weng, Li-De Chen, Hao-Chien Cheng, An-You Zheng, Kai-Ping Lin, Chao-Tsung Huang. 1-3 [doi]
- A 0.385-pJ/bit 10-Gb/s TIA-Terminated Di-Code Transceiver with Edge-Delayed Equalization, ECC, and Mismatch Calibration for HBM InterfacesHyunsu Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Junyoung Song, Chulwoo Kim. 1-3 [doi]
- A Highly Power Efficient 2×3 PIN-Diode-Based Intercoupled THz Radiating Array at 425GHz with 18.1dBm EIRP in 90nm SiGe BiCMOSSam Razavian, Aydin Babakhani. 1-3 [doi]
- Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNetKazutoshi Hirose, Jaehoon Yu, Kota Ando, Yasuyuki Okoshi, Ángel López García-Arias, Junnosuke Suzuki, Thiem Van Chu, Kazushi Kawamura, Masato Motomura. 1-3 [doi]
- A 2.6mW 10pTI √ Hz 33kHz Magnetoimpedance-Based Magnetometer with Automatic Loop-Gain and Bandwidth EnhancementIppei Akita, Takeshi Kawano, Hitoshi Aoyama, Shunichi Tatematsu, Masakazu Hioki. 1-3 [doi]
- A -91 dB THD+N Resistor-Less Class-D Piezoelectric Speaker Driver Using a Dual Voltage/ Current Feedback for LC Resonance DampingShoubhik Karmakar, Marco Berkhout, Kofi A. A. Makinwa, Qinwen Fan. 1-3 [doi]
- A MEMS Coriolis-Based Mass-Flow-to-Digital Converter with 100µg/h/√Hz Noise i Floor and Zero Stability of ±0.35mg/hArthur C. de Oliveira, Sining Pan, Kofi A. A. Makinwa. 1-3 [doi]
- A 56GHz 23mW Fractional-N PLL with 110fs JitterYu Zhao, Onur Memioglu, Behzad Razavi. 1-3 [doi]
- A 121.4dB DR, -109.8dB THD+N Capacitively-Coupled Chopper Class-D Audio AmplifierHuajun Zhang, Marco Berkhout, Kofi A. A. Makinwa, Qinwen Fan. 1-3 [doi]
- A 68.3% Efficiency Reconfigurable 400-/800-mW Capacitive Isolated DC-DC Converter with Common-Mode Transient Immunity and Fast Dynamic Response by Through-Power-Link Hysteretic ControlJunyao Tang, Lei Zhao, Cheng Huang. 1-3 [doi]
- A 16-Channel, 28/39GHz Dual-Polarized 5G FR2 Phased-Array Transceiver IC with a Quad-Stream IF Transceiver Supporting Non-Contiguous Carrier Aggregation up to 1.6GHz BWAshutosh Verma, Venumadhav Bhagavatula, Amitoj Singh, Wanghua Wu, Hariharan Nagarajan, Pak-Kim Lau, Xiaohua Yu, Omar Elsayed, Ajaypat Jain, Anirban Sarkar, Fan Zhang, Che-Chun Kuo, Patrick McElwee, Pei-Yuan Chiang, Chengkai Guo, Zhanjun Bai, Tienyu Chang, Abishek Mann, Andreas Rydin, Xingliang Zhao, Jeiyoung Lee, Daeyoung Yoon, Chih-Wei Yao, Siuchuang-Ivan Lu, Sang-Won Son, Thomas Byunghak Cho. 1-3 [doi]
- 26.2 Design Considerations for Superconducting Quantum SystemsGeorge Zettles, Scott Willenborg, Blake R. Johnson, Andrew Wack, Brian Allison. 1-3 [doi]
- An 8-Mb DC-Current-Free Binary-to-8b Precision ReRAM Nonvolatile Computing-in-Memory Macro using Time-Space-Readout with 1286.4-21.6TOPS/W for Edge-AI DevicesJe-Min Hung, Yen-Hsiang Huang, Sheng-Po Huang, Fu-Chun Chang, Tai-Hao Wen, Chin-I Su, Win-San Khwa, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang. 1-3 [doi]
- A 100MHz-Reference, 8GHz/16GHz, 177fsrms/223fsrms RO-Based IL-ADPLL Incorporating Reference Octupler with Probability-Based Fast Phase-Error CalibrationHyojun Kim, Hyeong-Seok Oh, Woosong Jung, Yoonho Song, Jonghyun Oh, Deog Kyoon Jeong. 1-3 [doi]
- rms-Total-integrated-Jitter and 1.5µs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency SwitchingSimone Mattia Dartizio, Francesco Buccoleri, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino. 1-3 [doi]
- 20.5mW 0.28ppm Frequency Deviation Pixel-level Readout for Zeptogram Gravimetric SensingGérard Billiot, Paul Mattei, Bogdan Vysotskyi, Adrien Reynaud, Louis Hutin, Christophe Plantier, Emmanuel Rolland, Marc Gely, Giulia Usai, Claude Tabone, Gaël Pillonnet, Stéphanie Robinet, Sébastien Hentz. 1-3 [doi]
- COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine LearningHaozhe Zhu, Bo Jiao, Jinshan Zhang, Xinru Jia, Yunzhengmao Wang, Tianchan Guan, Shengcheng Wang, Dimin Niu, Hongzhong Zheng, Chixiao Chen, Mingyu Wang, Lihua Zhang, Xiaoyang Zeng, Qi Liu, Yuan Xie, Ming Liu. 1-3 [doi]
- A 64Mpixel CMOS Image Sensor with 0.50µm Unit Pixels Separated by Front Deep-Trench IsolationSungbong Park, ChangKyu Lee, Sangcheon Park, Haeyong Park, Taeheon Lee, Dami Park, Minsung Heo, Inyong Park, Hyunyoung Yeo, Youna Lee, Juhee Lee, Beomsuk Lee, Dong-Chul Lee, Jinyoung Kim, Bokwon Kim, Jinsun Pyo, Shili Quan, Sungyong You, Inho Ro, Sungsoo Choi, SungIn Kim, Insung Joe, JongEun Park, Chang-Hyo Koo, Jae-Ho Kim, Chong Kwang Chang, Taehee Kim, Jingyun Kim, Jamie Lee, Hyunchul Kim, Changrok Moon, Hyoung-Sub Kim. 1-3 [doi]
- A 1-to-18GHz Distributed-Stacked-Complementary Triple-Balanced Passive Mixer With up to 33dBm IIP3 and Integrated LO Driver in 45nm CMOS SOICameron Hill, James F. Buckwalter. 1-3 [doi]
- A Self-powering Wireless Soil-pH and Electrical Conductance Monitoring IC with Hybrid Microbial Electrochemical and Photovoltaic Energy HarvestingChuan-Yi Wu, Chi-Wei Liu, Jing Siang Chen, Cong-Sheng Huang, Ting-Heng Lu, Ling-Chia Chen, I-Che Ou, Sook-Kuan Lee, Yen-Chi Chen, Po-Hung Chen, Chi-Te Liu, Ying-Chih Liao, Yu-Te Liao. 1-3 [doi]
- A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI DevicesPing-Chun Wu, Jian-Wei Su, Yen-Lin Chung, Li-Yang Hong, Jin-Sheng Ren, Fu-Chun Chang, Yuan Wu, Ho-Yu Chen, Chen-Hsun Lin, Hsu-Ming Hsiao, Sih-Han Li, Shyh-Shyuan Sheu, Shih-Chieh Chang, Wei-Chung Lo, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Chih-I Wu, Meng-Fan Chang. 1-3 [doi]
- 2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write OperationsHidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao, Mei-Chen Chuang, Rawan Naous, Chao-Kai Chuang, Takeshi Hashizume, Dar Sun, Chia-Fu Lee, Kerem Akarvardar, Saman Adham, Tan-Li Chou, Mahmut Ersin Sinangil, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang. 1-3 [doi]
- A 97fsrms-Jitter and 68-Multiplication Factor, 8.16GHz Ring-Oscillator Injection-Locked Clock Multiplier with Power-Gating Injection-Locking and Background Multi-Functional Digital CalibratorSuneui Park, Seyeon Yoo, Yuhwan Shin, Jeonghyun Lee, Jaehyouk Choi. 1-3 [doi]
- A 27W D2D Wireless Power Transfer System with Compact Single-Stage Regulated Class-E Architecture and Adaptive ZVS ControlXiaofei Ma, Yan Lu 0002, Wing-Hung Ki. 1-3 [doi]
- A Miniaturized Wireless Neural Implant with Body-Coupled Data Transmission and Power Delivery for Freely Behaving AnimalsChanguk Lee, Byeongseol Kim, Jejung Kim, Sangwon Lee, Taejune Jeon, Woojun Choi, Sunggu Yang, Jong-Hyun Ahn, Joonsung Bae, Youngcheol Chae. 1-3 [doi]
- Series-Resonance BiCMOS VCO with Phase Noise of -138dBc/Hz at 1MHz Offset from 10GHz and -190dBc/Hz FoMAlessandro Franceschin, Domenico Riccardi, Andrea Mazzanti. 1-3 [doi]
- A 430GHz CMOS Concurrent Transceiver Pixel Array for High Angular Resolution Reflection-Mode Active ImagingYukun Zhu, Pranith R. Byreddy, Shenggang Dong, Kenneth K. O, Wooyeol Choi 0001. 1-3 [doi]
- A 28nm 29.2TFLOPS/W BF16 and 36.5TOPS/W INT8 Reconfigurable Digital CIM Processor with Unified FP/INT Pipeline and Bitwise In-Memory Booth Multiplication for Cloud Deep Learning AccelerationFengbin Tu, Yiqi Wang 0005, Zihan Wu, Ling Liang, Yufei Ding, Bongjin Kim, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin. 1-3 [doi]
- FlexSpin: A Scalable CMOS Ising Machine with 256 Flexible Spin Processing Elements for Solving Complex Combinatorial Optimization ProblemsYuqi Su, Tony Tae-Hyoung Kim, Bongjin Kim. 1-3 [doi]
- A 50Gb/s PAM-4 Bi-Directional Plastic Waveguide Link with Carrier Synchronization Using PI-Based Costas LoopHa-II Song, Hanho Choi, Jun Young Yoo, Hyosup Won, Cheong Min Lee, Huxian Jin, Tai Young Kim, Woohyun Kwon, Kyoohyun Lim, Konan Kwon, Chang-Ahn Kim, Taeho Kim, Jun-Gi Jo, Jake Eu, Sean Park, Hyeon-Min Bae. 1-3 [doi]
- 23D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation SystemDimin Niu, Shuangchen Li, Yuhao Wang, Wei Han, Zhe Zhang, Yijin Guan, Tianchan Guan, Fei Sun, Fei Xue, Lide Duan, Yuanwei Fang, Hongzhong Zheng, Xiping Jiang, Song Wang, Fengguo Zuo, Yubing Wang, Bing Yu, Qiwei Ren, Yuan Xie. 1-3 [doi]
- A 23μW Solar-Powered Keyword-Spotting ASIC with Ring-Oscillator-Based Time-Domain Feature ExtractionKwantae Kim, Chang Gao, Rui Graça, Ilya Kiselev, Hoi-Jun Yoo, Tobi Delbrück, Shih-Chii Liu. 1-3 [doi]
- A 9b-Linear 14GHz Integrating-Mode Phase Interpolator in 5nm FinFET ProcessAmit Kumar Mishra, Yifei Li, Pawan Agarwal, Sudip Shekhar. 1-3 [doi]
- A Broadband Mm-Wave VSWR-Resilient Joint True-Power Detector and Impedance Sensor Supporting Single-Ended Antenna InterfacesDavid Joseph Munzer, Naga Sasikanth Mannem, Edgar Felipe Garay, Hua Wang. 1-3 [doi]
- TM ProcessorBrian T. Vanderpool, Phillip J. Restle, Eric J. Fluhr, Gregory S. Still, Frank Campisano, Ian Carmichael, Eric Marz, Rahul Batra, Richard L. Willaman. 1-3 [doi]
- 5 Dynamic Range, Integrated MPPT, and Multi-Modal Cold Start-UpShuo Li 0008, Xinjian Liu, Benton H. Calhoun. 1-3 [doi]
- A 65nm Systolic Neural CPU Processor for Combined Deep Learning and General-Purpose Computing with 95% PE Utilization, High Data Locality and Enhanced End-to-End PerformanceYuhao Ju, Jie Gu 0001. 1-3 [doi]
- A 28nm 27.5TOPS/W Approximate-Computing-Based Transformer Processor with Asymptotic Sparsity Speculating and Out-of-Order ComputingYang Wang, Yubin Qin, Dazheng Deng, Jingchuan Wei, Yang Zhou, Yuanqi Fan, Tianbao Chen, Hao Sun, Leibo Liu, Shaojun Wei, Shouyi Yin. 1-3 [doi]
- A 40-nm, 2M-Cell, 8b-Precision, Hybrid SLC-MLC PCM Computing-in-Memory Macro with 20.5 - 65.0TOPS/W for Tiny-Al Edge DevicesWin-San Khwa, Yen-Cheng Chiu, Chuan-Jia Jhang, Sheng-Po Huang, Chun-Ying Lee, Tai-Hao Wen, Fu-Chun Chang, Shao-Ming Yu, Tung-Yin Lee, Meng-Fan Chang. 1-3 [doi]
- A 480-Multiplication-Factor 13.2-to-17.3GHz Sub-Sampling PLL Achieving 6.6mW Power and -248.1 dB FoM Using a Proportionally Divided Charge PumpLuya Zhang, Ali M. Niknejad. 1-3 [doi]
- ReckOn: A 28nm Sub-mm2 Task-Agnostic Spiking Recurrent Neural Network Processor Enabling On-Chip Learning over Second-Long TimescalesCharlotte Frenkel, Giacomo Indiveri. 1-3 [doi]
- , Fully Integrated Multi-Phase Voltage Regulator with 91.5% Peak Efficiency at 1.8 to 1V, Operating at 50MHz and Featuring a Digitally Assisted Controller with Automatic Phase Shedding and Soft Switching in 4nm Class FinFET CMOSChristopher Schaef, Tamir Salus, Rachid Rayess, Siddarth Kulasekaran, Mat Manusharow, Kaladhar Radhakrishnan, Jonathan Douglas. 1-3 [doi]
- A Second-Order Temperature-Compensated On-Chip R-RC Oscillator Achieving 7.93ppm/°C and 3.3pJ/Hz in -40°C to 125°C Temperature RangeYoungwoo Ji, Jiawei Liao, Sina Arjmandpour, Alessandro Novello, Jae-Yoon Sim, Taekwang Jang. 1-3 [doi]
- A 0.97mW 260MS/s 12b Pipelined-SAR ADC with Ring-TDC-Based Fine Quantizer for PVT Robust Automatic Cross-Domain Scale AlignmentHaoyi Zhao, Fa Foster Dai. 1-3 [doi]
- A 1ynm 1.25V 8Gb, 16Gb/s/pin GDDR6-based Accelerator-in-Memory supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep-Learning ApplicationsSeong Ju Lee, Kyu-Young Kim, Sanghoon Oh, Joonhong Park, Gimoon Hong, Dong Yoon Ka, Kyu-Dong Hwang, Jeongje Park, Kyeong Pil Kang, Jungyeon Kim, Junyeol Jeon, Nahsung Kim, Yongkee Kwon, Kornijcuk Vladimir, Woojae Shin, Jongsoon Won, Minkyu Lee, Hyunha Joo, Haerang Choi, Jaewook Lee, Donguc Ko, Younggun Jun, Keewon Cho, Ilwoong Kim, Choungki Song, Chunseok Jeong, Dae-Han Kwon, Jieun Jang, Il Park 0001, Junhyun Chun, Joohwan Cho. 1-3 [doi]
- A 110V/230V 0.3W Offline Chip-Scale Power Supply with Integrated Active Zero-Crossing Buffer and Voltage-Interval-Based Dual-Mode ControlChristoph Rindfleisch, Bernhard Wicht. 1-3 [doi]
- A 200 x 256 Image Sensor Heterogeneously Integrating a 2D Nanomaterial-Based Photo-FET Array and CMOS Time-to-Digital ConvertersHenry Hinton, Houk Jang, Wenxuan Wu, Min-Hyun Lee, Minsu Seol, Hyeon-Jin Shin, Seongjun Park, Donhee Ham. 1-3 [doi]
- A Monolithic GaN Direct 48V/1V AHB Switching Power IC with Auto-Lock Auto-Break Level Shifting, Self-Bootstrapped Hybrid Gate Driving, and On-Die Temperature SensingDong Yan, Dongsheng Brian Ma. 1-3 [doi]
- A 40nm 60.64TOPS/W ECC-Capable Compute-in-Memory/Digital 2.25MB/768KB RRAM/SRAM System with Embedded Cortex M3 Microprocessor for Edge Recommendation SystemsMuya Chang, Samuel D. Spetalnick, Brian Crafton, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury. 1-3 [doi]
- A 1-58.125Gb/s, 5-33dB IL Multi-Protocol Ethernet-Compliant Analog PAM-4 Receiver with 16 DFE Taps in 10nmBahram Zand, Mike Bichan, Alireza Mahmoodi, Mansour Shashaani, Jing Wang, Ruslana Shulyzki, James Guthrie, Katya Tyshchenko, Junhong Zhao, Eric Liu, Nima Soltani, Al Freeman, Rishi Anand, Syed Rubab, Ranjit Khela, Shaham Sharifian, Karl Herterich. 1-3 [doi]
- m BoostingZhe Liu, Chirn Chye Boon, Chenyang Li, Kaituo Yang, Yangtao Dong, Ting Guo. 1-3 [doi]
- A Fully Digital Time-Mode CMOS Image Sensor with 22.9pJ/frame.pixel and 92dB Dynamic RangeSangwoo Kim, Taehyoung Kim, Kiwon Seo, Gunhee Han. 1-3 [doi]
- 2 83.7%-Efficiency 400MHz 6-Phase Fully Integrated Buck Converter in 28nm CMOS with On-Chip Capacitor Dynamic Re-Allocation for Inter-Inductor Current Balancing and Fast DVS of 75mV/nsJeong-Hyun Cho, Dong-Kyu Kim, Hong-Hyun Bae, Yong-Jin Lee, Seok-Tae Koh, Young-Hwan Choo, Ji-Seon Paek, Hyun-Sik Kim. 1-3 [doi]
- A 300GHz 52mW CMOS Receiver with On-Chip LO GenerationOnur Memioglu, Yu Zhao, Behzad Razavi. 1-3 [doi]
- 2RRAM Binary/Compute-in-Memory Macro with 4.23x Improvement in Density and >75% Use of Sensing Dynamic RangeSamuel D. Spetalnick, Muya Chang, Brian Crafton, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury. 1-3 [doi]
- Electronic THz Pencil Beam Forming and 2D Steering for High Angular-Resolution Operation: A 98×98-Unit 265GHz CMOS Reflectarray with In-Unit Digital Beam Shaping and Squint CorrectionNathan M. Monroe, Georgios C. Doqiamis, Robert Stingel, Preston Myers, Xibi Chen, Ruonan Han 0001. 1-3 [doi]
- A 2-5MHz Multiple DC Output Hybrid Boost Converter with Scalable CR Boosting Scheme Achievi 1 ng 91% Efficie 1 ncy at a Conversion Ratio of 12Chen Chen, Jin Liu, Hoi Lee. 1-3 [doi]
- Side-Channel Attack Counteraction via Machine Learning-Targeted Power Compensation for Post-Silicon HW Security PatchingQiang Fang, Longyang Lin, Yao Zu Wong, Hui Zhang, Massimo Alioto. 1-3 [doi]
- PPKyu-Jin Choi, Jae-Yoon Sim. 1-3 [doi]
- A in 22nm FinFETJiang Gong, Bishnu Patra, Luc Enthoven, Job van Staveren, Fabio Sebastiano, Masoud Babaie. 1-3 [doi]
- 2-Tx Digital Envelope-Tracking Supply Modulator Achieving 200MHz Channel Bandwidth and 93.6% Efficiency for 2G/3G/LTE/NR RF Power AmplifiersJun-Suk Bang, Dongsu Kim, Jeongkwang Lee, Sung-Youb Jung, Young-Hwan Choo, Seungchan Park, Young-Ho Jung, Jae-Young Ko, Takahiro Norniyama, Jongbeom Baek, Jae-Yeol Han, Sang-Han Lee, Ik-Hwan Kim, Ji-Seon Paek, Jongwoo Lee, Thomas Byunghak Cho. 1-3 [doi]
- A 210×340×50µm Integrated CMOS System f0r Micro-Robots with Energy Harvesting, Sensing, Processing, Communication and ActuationLi Xu 0006, Maya Lassiter, Xiao Wu 0002, Yejoong Kim, Jungho Lee, Makoto Yasuda, Masaru Kawaminami, Marc Miskin, David T. Blaauw, Dennis Sylvester. 1-3 [doi]
- A 174μVRMS Input Noise, 1 G8/s Comparator in 22nm FDSOI with a Dynamic-Bias Preamplifier Using Tail Charge Pump and Capacitive Neutralization Across the LatchHarijot Singh Bindra, Jeroen Ponte, Bram Nauta. 1-3 [doi]
- DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoCKodai Ueyoshi, Ioannis A. Papistas, Pouya Houshmand, Giuseppe M. Sarda, Vikram Jain, Man Shi, Qilin Zheng, Juan Sebastian P. Giraldo, Peter Vrancx, Jonas Doevenspeck, Debjyoti Bhattacharjee, Stefan Cosemans, Arindam Mallik, Peter Debacker, Diederik Verkest, Marian Verhelst. 1-3 [doi]
- A 145.2dB-DR Baseline-Tracking Impedance Plethysmogram IC for Neckband-Based Blood Pressure and Cardiovascular MonitoringChan Sam Park, Hyunjoong Kim, Kwangmuk Lee, Dae Sik Keum, Dong Pyo Jang, Jae-Joon Kim. 1-3 [doi]
- A 1-Tb Density 4b/Cell 3D-NAND Flash on 176-Tier Technology with 4-Independent Planes for Read using CMOS-Under-the-ArrayTed Pekny, Luyen Vu, Jeffrey Tsai, Dheeraj Srinivasan, Erwin Yu, Jonathan Pabustan, Joe Xu, Srinivas Deshmukh, Kim-Fung Chan, Michael Piccardi, Kevin Xu, Guan Wang, Kaveh Shakeri, Vipul Patel, Tomoko Iwasaki, Tongji Wang, Padma Musunuri, Carl Gu, Ali Mohammadzadeh, Ali Ghalam, Violante Moschiano, Tommaso Vali, Jae-Kwan Park, June Lee, Ramin Ghodsi. 1-3 [doi]
- 2 Analog Voice Activity Detector (VAD) Featuring a Time-Domain CNN as a Programmable Feature Extractor and a Sparsity-Aware Computational Scheme in 28nm CMOSFeifei Chen, Ka-Fai Un, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins. 1-3 [doi]
- An 8.3-to-18Gbps Reconfigurable SCA-Resistant/Dual-Core/Blind-Bulk AES Engine in Intel 4 CMOSRaghavan Kumar, Vikram B. Suresh, Mark A. Anders 0001, Steven K. Hsu, Amit Agarwal 0001, Vivek K. De, Sanu K. Mathew. 1-3 [doi]
- A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference SpurTsung-Hsien Tsai, Ruey-Bin Sheen, Sheng-Yun Hsu, Ya-Tin Chang, Chih-Hsien Chang, Robert Bogdan Staszewski. 1-3 [doi]
- A 0.8V Intelligent Vision Sensor with Tiny Convolutional Neural Network and Programmable Weights Using Mixed-Mode Processing-in-Sensor Technique for Image ClassificationTzu-Hsiang Hsu, Guan-Cheng Chen, Yi Ren Chen, Chung-Chuan Lo, Ren-Shuo Liu, Meng-Fan Chang, Kea-Tiong Tang, Chih-Cheng Hsieh. 1-3 [doi]
- An Optimal Digital Beamformer for mm-Wave Phased Arrays with 660MHz Instantaneous Bandwidth in 28nm CMOSDiego Peña-Colaiocco, Chi-Hsiang Huang 0001, Kun-Da Chu, Jacques Christophe Rudell, Visvesh S. Sathe 0001. 1-3 [doi]
- A 194nW Energy-Performance-Aware loT SoC Employing a 5.2nW 92.6% Peak Efficiency Power Management Unit for System Performance Scaling, Fast DVFS and Energy MinimizationXinjian Liu, Sumanth Kamineni, Jacob Breiholz, Benton H. Calhoun, Shuo Li 0008. 1-3 [doi]
- A 4A 12-to-1 Flying Capacitor Cross-Connected DC-DC Converter with Inserted D>0.5 Control Achieving >2x Transient Inductor Current Slew Rate and 0.73× Theoretical Minimum Output Undershoot of DSDTingxu Hu, Mo Huang, Yan Lu 0002, Rui Paulo Martins. 1-3 [doi]
- 2 10kHz-BW Zoom-Incremental-Counting ADC Achieving 103dB SNDR and 100dB Full-Scale CMRRLu Jie, Mingtao Zhan, Xiyuan Tang, Nan Sun. 1-3 [doi]
- A 12V/24V-to-1V DSD Power Converter with 56mV Droop and 0.9µS 1% Settling Time for a 3A/20ns Load TransientJingyi Yuan, Zeguo Liu, Feng Wu, Lin Cheng. 1-3 [doi]
- Catalyzing the Impossible: Silicon, Software, and Smarts for the SysMoore EraAart De Geus. 10-16 [doi]
- Intelligent Sensing: Enabling the Next "Automation Age"Marco Cassis. 17-24 [doi]
- The Art of Scaling: Distributed and Connected to Sustain the Golden Age of ComputationInyup Kang. 25-31 [doi]
- The Future of the High-Performance Semiconductor Industry and DesignRenee James. 32-35 [doi]
- Ponte Vecchio: A Multi-Tile 3D Stacked Processor for Exascale ComputingWilfred Gomes, Altug Koker, Patrick N. Stover, Doug B. Ingerly, Scott Siers, Srikrishnan Venkataraman, Chris Pelto, Tejas Shah, Amreesh Rao, Frank O'Mahony, Eric Karl, Lance Cheney, Iqbal Rajwani, Hemant Jain, Ryan Cortez, Arun Chandrasekhar, Basavaraj Kanthi, Raja Koduri. 42-44 [doi]
- Sapphire Rapids: The Next-Generation Intel Xeon Scalable ProcessorNevine Nassif, Ashley O. Munch, Carleton L. Molnar, Gerald Pasdast, Sitaraman V. Lyer, Zibing Yang, Oscar Mendoza, Mark Huddart, Srikrishnan Venkataraman, Sireesha Kandula, Rafi Marom, Alexandra M. Kern, William J. Bowhill, David R. Mulvihill, Srikanth Nimmagadda, Varma Kalidindi, Jonathan Krause, Mohammad M. Haq, Roopali Sharma, Kevin Duda. 44-46 [doi]
- IBM Telum: a 16-Core 5+ GHz DCMOfer Geva, Christopher J. Berry, Robert J. Sonnelitter, David Wolpert 0001, Adam Collura, Thomas Strach, Di Phan, Cédric Lichtenau, Alper Buyuktosunoglu, Hubert Harrer, Jeffrey A. Zitz, Chad Marquart, Douglas Malone, Tobias Webel, Adam Jatkowski, John Isakson, Dina Hamid, Mark Cichanowski, Michael Romain, Faisal Hasan, Kevin Williams, Jesse Surprise, Chris Cavitt, Mark Cohen. 46-48 [doi]
- POWER10™: A 16-Core SMT8 Server Processor With 2TB/s Off-Chip Bandwidth in 7nm TechnologyRahul M. Rao, Christopher J. Gonzalez, Eric Fluhr, Abraham Mathews, Andrew Bianchi, Daniel Dreps, David Wolpert 0001, Eric Lai, Gerald Strevig, Glen A. Wiedemeier, Philipp Salz, Ryan Kruse. 48-50 [doi]
- A 5nm 3.4GHz Tri-Gear ARMv9 CPU Subsystem in a Fully Integrated 5G Flagship Mobile SoCAshish Nayak, HsinChen Chen, Hugh Mair, Rolf Lagerquist, Tao Chen, Anand Rajagopalan, Gordon Gammie, Ramu Madhavaram, Madhur Jagota, C. J. Chung, Jenny Wiedemeier, Bala Meera, Chao-Yang Yeh, Maverick Lin, Curtis Lin, Vincent Lin, Jiun Lin, Y. S. Chen, Barry Chen, Cheng-Yuh Wu, Ryan ChangChien, Ray Tzeng, Kelvin Yang, Achuta Thippana, Ericbill Wang, Shih-Arn Hwang. 50-52 [doi]
- A 16nm 785GMACs/J 784-Core Digital Signal Processor Array With a Multilayer Switch Box Interconnect, Assembled as a 2×2 Dielet with 10μm-Pitch Inter-Dielet I/O for Runtime Multi-Program ReconfigurationUneeb Rathore, Sumeet Singh Nagi, Subramanian Iyer, Dejan Markovic. 52-54 [doi]
- A Single-Crystal-Oscillator-Based Clock-Management IC with 18× Start-Up Time Reduction and 0.68ppm/ºC Duty-Cycled Machine-Learning-Based RCO CalibrationJaehong Jung, Seunghyun Oh, Joo-Myoung Kim, Gihyeok Ha, Jinhyeon Lee, Seungjin Kim, Euiyoung Park, Jaehoon Lee, Yelim Yoon, Seungyong Bae, Wonkang Kim, Yong Lim, Kyungsoo Lee, Junho Huh, Jongwoo Lee, Thomas Byunghak Cho. 58-60 [doi]
- A 52MHz -158.2dBc/Hz PN @ 100kHz Digitally Controlled Crystal Oscillator Utilizing a Capacitive-Load-Dependent Dynamic Feedback Resistor in 28nm CMOSJaehong Jung, Seungjin Kim, Wonkang Kim, Jae-Yeol Han, Euiyoung Park, Seongwook Hwang, Seunghyun Oh, Sangwook Han, Kyungsoo Lee, Junho Huh, Jongwoo Lee. 60-62 [doi]
- A ±25A Versatile Shunt-Based Current Sensor with 10kHz Bandwidth and ±0.25% Gain Error from -40°C to 85°C Using 2-Current CalibrationZhong Tang, Roger Zarnparette, Yoshikazu Furuta, Tomohiro Nezuka, Kofi A. A. Makinwa. 66-68 [doi]
- 2 at 150°CBo Wang, Man Kay Law, Amine Bermak. 72-74 [doi]
- Fully Integrated 2D Scalable TX/RX Chipset for D-Band Phased-Array-on-Glass ModulesMohamed Elkhouly, Jaegeun Ha, Michael J. Holyoak, David Hendry, Mustafa Sayginer, Ryan Enright, Ioannis Kimionis, Yves Baeyens, Shahriar Shahramian. 76-78 [doi]
- A Fully Integrated 160Gb/s D-Band Transmitter with 1.1 pJ/b Efficiency in 22nm FinFET TechnologySteven Callender, Amy Whitcombe, Abhishek Agrawal, Ritesh Bhat, Mustafijur Rahman, Chun C. Lee, Peter Sagazio, Georgios Dogiamis, Brent R. Carlton, Mark Chakravorti, Stefano Pellerano, Christopher D. Hull. 78-80 [doi]
- A 140GHz Transceiver with Integrated Antenna, Inherent-Low-Loss Duplexing and Adaptive Self-Interference Cancellation for FMCW Monostatic RadarXibi Chen, Muhammad Ibrahim Wasiq Khan, Xiang Yi, Xingcun Li, Wenhua Chen, Jianfeng Zhu, Yang Yang, Kenneth E. Kolodziej, Nathan M. Monroe, Ruonan Han 0001. 80-82 [doi]
- A 23-to-29GHz Receiver with mm-Wave N-Input-N-Output Spatial Notch Filtering and Autonomous Notch-Steering Achieving 20-to-40dB mm-Wave Spatial Rejection and -14dBm In-Notch IP1 dBLinghan Zhang, Masoud Babaie. 82-84 [doi]
- A 3.4mW/element Radiation-Hardened Ka-Band CMOS Phased-Array Receiver Utilizing Magnetic-Tuning Phase Shifter for Small Satellite ConstellationXi Fu, Yun Wang, Dongwon You, Xiaolin Wang, Ashbir Aviat Fadila, Yi Zhang, Sena Kato, Chun Wang, Zheng Li, Jian Pang, Atsushi Shirane, Kenichi Okada. 90-92 [doi]
- A 0.37W 143dB-Dynamic-Range 1Mpixel Backside-Illuminated Charge-Focusing SPAD Image Sensor with Pixel-Wise Exposure Control and Adaptive Clocked RechargingYasuharu Ota, Kazuhiro Morimoto, Tomoya Sasago, Mahito Shinohara, Yukihiro Kuroda, Wataru Endo, Yu Maehashi, Shintaro Maekawa, Hiroyuki Tsuchiya, Aymantarek Abdelahafar, Shingo Hikosaka, Masanao Motoyama, Kenzo Tojima, Kosei Uehira, Junji Iwata, Fumihiro Inui, Yasushi Matsuno, Katsuhito Sakurai, Takeshi Ichikawa. 94-96 [doi]
- A 64×64-Pixel Flash LiDAR SPAD Imager with Distributed Pixel-to-Pixel Correlation for Background Rejection, Tunable Automatic Pixel Sensitivity and First-Last Event Detection Strategies for Space ApplicationsEnrico Manuzzato, Alessandro Tontini, Andrej Seljak, Matteo Perenzoni. 96-98 [doi]
- An 80×60 Flash LiDAR Sensor with In-Pixel Histogramming TDC Based on Quaternary Search and Time-Gated Δ-Intensity Phase Detection for 45m Detectable Range and Background Light CancellationSeonghyeok Park, Bumjun Kim, Junhee Cho, Jung-Hoon Chun, Jaehyuk Choi, Seong-Jin Kim. 98-100 [doi]
- A 38µm Range Precision Time-of-Flight CMOS Range Line Imager with Gating Driver Jitter Reduction Using Charge-Injection Pseudo Photocurrent ReferenceKeita Yasutomi, Tatsuki Furuhashi, Koki Sagawa, Taishi Takasawa, Keiichiro Kagawa, Shoji Kawahito. 100-102 [doi]
- A 1/1.57-inch 50Mpixel CMOS Image Sensor With 1.0μm All-Directional Dual Pixel by 0.5μm-Pitch Full-Depth Deep-Trench Isolation TechnologyTaesub Jung, Masato Fujita, Jeongjin Cho, Kyungduck Lee, Doosik Seol, Sungmin An, Chanhee Lee, Youjin Jeong, Minji Jung, Sachoun Park, Seungki Baek, Seungki Jung, Seunghwan Lee, Jungbin Yun, Eun Sub Shim, Heetak Han, Eunkyung Park 0003, Haesick Sul, Sehyeon Kang, Kyungho Lee, JungChak Ahn, Duckhyun Chang. 102-104 [doi]
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- A 5V Input 98.4% Peak Efficiency Reconfigurable Capacitive-Sigma Converter With Greater than 90% Peak Efficiency for the Entire 0.4~1.2V Output RangeXu Yang, Linhu Zhao, Menglian Zhao, Zhichao Tan, Lenian He, Yong Ding 0003, Wuhua Li, Wanyuan Qu. 108-110 [doi]
- 2/channel and 4.8mV DVO for Mobile OLED DisplaysGyu-Wan Lim, Gyeong-Gu Kang, Hyunggun Ma, Moonjae Jeong, Hyun-Sik Kim. 110-112 [doi]
- A 1.41pJ/b 224Gb/s PAM-4 SerDes Receiver with 31dB Loss CompensationYoav Segal, Amir Laufer, Ahmad Khairi, Yoel Krupnik, Marco Cusmai, Itamar Levin, Ari Gordon, Yaniv Saban, Vitali Rahinskj, Gadi Ori, Noam Familia, Stas Litski, Tali Warshavsky, Udi Virobnik, Yeshayahu Horwitz, Ajay Balankutty, Shiva Kiran, Samuel Palermo, Peng Mike Li, Ariel Cohen 0001. 114-116 [doi]
- A 112.5Gb/s ADC-DSP-Based PAM-4 Long-Reach Transceiver with >50dB Channel Loss in 5nm FinFETZ. Guo, A. Mostafa, A. Elshazly, B. Chen, B. Wang, C. Han, C. Wang, D. Zhou, D. Visani, E. Hsiao, F. Chu, F. Lu, G. Cui, H. Zhang, H. Wang, H. Zhao, J. Lin, J. Gu, L. Luo, L. Jiang, M. Singh, M. Gambhir, M. Hasan, M. Wu, M.-J. Yoo, P. Liu, S. Kollu, T. Ye, X. Zhao, X. Yang, X. Han, Y. Huang, Y. Sun, Z. Yu, Z. H. Jiang, Z. Adal, Z. Yan. 116-118 [doi]
- A 2.29pJ/b 112Gb/s Wireline Transceiver with RX 4-Tap FFE for Medium-Reach Applications in 28nm CMOSBingyi Ye, Kai Sheng, Weixin Gai, Haowei Niu, Boyang Zhang, YanDong He, Song Jia, Congcong Chen, Jiaqi Yu. 118-120 [doi]
- An 182mW 1-60Gb/s Configurable PAM-4/NRZ Transceiver for Large Scale ASIC Integration in 7nm FinFET TechnologyNamik Kocaman, Ullas Singh, Bharath Raghavan, Arvindh Iyer, Kumar Thasari, Saurabh Surana, Jun Won Jung, Jaehun Jeong, Heng Zhang, Anand Vasani, Yonghyun Shim, Zhi Huang, Adesh Garg, Hsiang-bin Lee, Bo Wu, Feifei Liu, Ray Wang, Matthew Loh, Alex Wang, Mario Caresosa, Bo Zhang 0029, Afshin Momtaz. 120-122 [doi]
- A 1.6Tb/s Chiplet over XSR-MCM Channels using 113Gb/s PAM-4 Transceiver with Dynamic Receiver-Driven Adaptation of TX-FFE and Programmable Roaming Taps in 5nm CMOSGautam Reddy Gangasani, D. Hanson, Daniel W. Storaska, H. H. Xu, M. Kelly, M. Shannon, Michael Sorna, Michael Wielgos, P. B. Ramakrishna, S. Shi, S. Parker, U. K. Shukla, W. Kelly, W. Su, Z. Yu. 122-124 [doi]
- A 1-Tb 4b/Cell 4-Plane 162-Layer 3D Flash Memory With a 2.4-Gb/s I/O Speed InterfaceJong Yuh, Jason Li 0001, Heguang Li, Yoshihiro Oyama, Cynthia Hsu, Pradeep Anantula, Stanley Jeong, Anirudh Amarnath, Siddhesh Darne, Sneha Bhatia, Tianyu Tang, Aditya Arya, Naman Rastogi, Naoki Ookuma, Hiroyuki Mizukoshi, Alex Yap, Demin Wang, Steve Kim, Yonggang Wu, Min Peng, Jason Lu, Tommy Ip, Seema Malhotra, David Han, Masatoshi Okumura, Jiwen Liu, John Sohn, Hardwell Chibvongodze, Muralikrishna Balaga, Aki Matsuda, Chakshu Puri, Chen Chen, Indra K. V, Chaitanya G, Venky Ramachandra, Yosuke Kato, Ravi Kumar, Huijuan Wang, Farookh Moogat, In-Soo Yoon, Kazushige Kanda, Takahiro Shimizu, Noboru Shibata, Takashi Shigeoka, Kosuke Yanagidaira, Takuyo Kodama, Ryo Fukuda, Yasuhiro Hirashima, Mitsuhiro Abe. 130-132 [doi]
- A 1-Tb, 4b/Cell, 176-Stacked-WL 3D-NAND Flash Memory with Improved Read Latency and a 14.8Gb/mm2 DensityWanik Cho, Jongseok Jung, Jongwoo Kim, Junghoon Nam, Sangkyu Lee, Yujong Noh, Dauni Kim, Wanseob Lee, Kayoung Cho, Kwanho Kim, Heejoo Lee, Sooyeol Chai, Eunwoo Jo, Hanna Cho, Jong-Seok Kim, Chankeun Kwon, Cheolioona Park, Hveonsu Nam, Haeun Won, Taeho Kim, Kyeonghwan Park, Sanghoon Oh, Jinhyun Ban, Junyoung Park, Jae-Hyeon Shin, Taisik Shin, Junseo Jang, Jiseong Mun, Jehyun Choi, Hyunseung Choi, Sung-Wook Choi, Wonsun Park, Dongkvu Yoon, Minsu Kim, Junyoun Lim, Chiwook An, Hyunyoung Shirr, Haesoon Oh, Haechan Park, Sungbo Shim, Hwang Huh, Honasok Choi, Seungpil Lee, Jaesuna Sim, Kichan Gwon, Jumsoo Kim, Woopyo Jeong, Jungdal Choi, Kyowon Jin. 134-135 [doi]
- A 1Tb 3b/Cell 8th-Generation 3D-NAND Flash Memory with 164MB/s Write Throughput and a 2.4Gb/s InterfaceMoosung Kim, Sung-Won Yun, Jungjune Park, Hyun Kook Park, Jungyu Lee, Yeong Seon Kim, Dae-Hoon Na, Sara Choi, Youngsun Song, Jonghoon Lee, Hyun-Jun Yoon, Kangbin Lee, Byunghoon Jeong, Sanglok Kim, Junhong Park, Cheon An Lee, Jaeyun Lee, Ji-Sang Lee, Jin-Young Chun, Joonsuc Jang, Younghwi Yang, Seung-Hyun Moon, Myung-Hoon Choi, Wontae Kim, Jungsoo Kim, Seok Min Yoon, Pansuk Kwak, Myunghun Lee, Raehyun Song, Sunghoon Kim, Chiweon Yoon, Dongku Kang, Jin-yub Lee, Jai Hyuk Song. 136-137 [doi]
- A 512Gb In-Memory-Computing 3D-NAND Flash Supporting Similar-Vector-Matching Operations on Edge-AI DevicesHan-Wen Hu, Wei-Chen Wang, Chung Kuang Chen, Yung-Chun Lee, Bo-Rong Lin, Huai-Mu Wang, Yen-Po Lin, Yu-Chao Lin, Chih-Chang Hsieh, Chia-Ming Hu, Yi-Ting Lai, Han-Sung Chen, Yuan-Hao Chang 0001, Hsiang-Pang Li, Tei-Wei Kuo, Keh-Chung Wang, Meng-Fan Chang, Chun-Hsiung Hung, Chih-Yuan Lu. 138-140 [doi]
- A 2-to-2.48GHz Voltage-Interpolator-Based Fractional-N Type-I Sampling PLL in 22nm FinFET Assisting Fast Crystal StartupSomnath Kundu, Timo Huusari, Hao Luo, Abhishek Agrawal, Eduardo Alban, Sarah Shahraini, Thao Xiong, Dan Lake, Stefano Pellerano, Jason Mix, Nasser A. Kurd, Mohamed Abdel-moneum, Brent R. Carlton. 144-146 [doi]
- A 9-to-12GHz Coupled-RTWO FMCW ADPLL with 97fs RMS Jitter, -120dBc/Hz PN at 1MHz Offset, and With Retrace Time of 12.5ns and 2μs Chirp Settling TimeHyman Shanan, Declan Dalton, Vamshi Chillara, Pablo Dato. 146-148 [doi]
- A 53.6-to-60.2GHz Many-Core Fundamental Oscillator With Scalable Mesh Topology Achieving -136.0dBc/Hz Phase Noise at 10MHz Offset and 190.3dBc/Hz Peak FoM in 65nm CMOSHaikun Jia, Ruichang Ma, Wei Deng 0001, Zhihua Wang 0001, Baoyong Chi. 154-156 [doi]
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- A 24b 2MS/s SAR ADC with 0.03ppm INL and 106.3dB DR in 180nm CMOSJesper Steensgaard, Richard Reay, Raymond Perry, Dave Thomas, Geoffrey Tu, George Reitsma. 168-170 [doi]
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- A Cryo-CMOS Low-Power Semi-Autonomous Qubit State Controller in 14nm FinFET TechnologyDavid J. Frank, Sudipto Chakraborty, Kevin Tien, Pat Rosno, Thomas Fox, Mark Yeck, Joseph A. Glick, Raphael Robertazzi, Ray Richetta, John F. Bulzacchelli, Daniel Ramirez, Dereje Yilma, Andrew Davies, Rajiv V. Joshi, Shawn D. Chambers, Scott Lekuch, Ken Inoue, Devin Underwood, Dorothy Wisnieff, Christian W. Baks, Donald Bethune, John Timmerwilke, Blake R. Johnson, Brian P. Gaucher, Daniel J. Friedman. 360-362 [doi]
- A Cryo-CMOS Controller IC With Fully Integrated Frequency Generators for Superconducting QubitsKiseo Kang, Donggyu Minn, Seunghun Bae, Jaeho Lee, Seongun Bae, Gichang Jung, Seokhyeong Kang, Moonjoo Lee, Ho-Jin Song, Jae-Yoon Sim. 362-364 [doi]
- A Cryogenic SiGe BiCMOS Hybrid Class B/C Mode-Switching VCO Achieving 201dBc/Hz Figure-of-Merit and 4.2GHz Frequency Tuning RangeYatao Peng, Andrea Ruffino, Jad Benserhir, Edoardo Charbon. 364-366 [doi]
- An 82nW 0.53pJ/SOP Clock-Free Spiking Neural Network with 40µs Latency for AloT Wake-Up Functions Using Ultimate-Event-Driven Bionic Architecture and Computing-in-Memory TechniqueYing Liu, Zhixuan Wang, Wei He, Linxiao Shen, Yihan Zhang, Peiyu Chen, Meng Wu, Hao Zhang, Peng Zhou, Jinguang Liu, Guangyu Sun, Jiayoon Ru, Le Ye, Ru Huang. 372-374 [doi]
- A 188fsrms-Jitter and -243d8-FoMjitter 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase SelectorChanwoong Hwang, Hangi Park, Taeho Seong, Jaehyouk Choi. 378-380 [doi]
- A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional SpursZhong Gao, Jingchu He, Martin Fritz, Jiang Gong, Yiyu Shen, Zhirui Zong, Peng Chen 0022, Gerd Spalink, Ben Eitel, Ken Yamamoto, Robert Bogdan Staszewski, Morteza S. Alavi, Masoud Babaie. 380-382 [doi]
- A Sub-100MHz Reference-Driven 25-to-28GHz Fractional-N PLL with -250dB FoMDihang Yang, David Murphy, Hooman Darabi, Arya Behzad, Asad A. Abidi, Stephen Au, Sraavan R. Mundlapudi, Kejian Shi, Weiyu Leng. 384-386 [doi]
- A 25.8GHz Integer-N PLL With Time-Amplifying Phase-Frequency Detector Achieving 60fsrms Jitter, -252.8dB FoMJ, and Robust Lock Acquisition PerformanceXinlin Geng, Yibo Tian, Yao Xiao, Zonglin Ye, Qian Xie, Zheng Wang. 388-390 [doi]
- A Long-Range Narrowband RF Localization System with a Crystal-Less Frequency-Hopping ReceiverChien-Wei Tseng, Demba Komma, Kuan-Yu Chen, Rohit Rothe, Zhen Feng, Makoto Yasuda, Masaru Kawaminami, Hun-Seok Kim, David T. Blaauw. 392-394 [doi]
- A 1.66Gb/s and 5.8pJ/b Transcutaneous IR-UWB Telemetry System with Hybrid Impulse Modulation for Intracortical Brain-Computer InterfacesMinyoung Song, Yu Huang, Yiyu Shen, Chengyao Shi, Arjan Breeschoten, Mario Konijnenburg, Huib Visser, Jac Romme, Barundeb Dutta, Morteza S. Alavi, Christian Bachmann, Yao-Hong Liu. 394-396 [doi]
- A 6.5-to-10GHz IEEE 802.15.4/4z-Compliant 1T3R UWB TransceiverRun Chen, Yuzhong Xiao, Yonggang Chen, Hua Xu, Peng Yu, Qi Peng, Xian Li, Xiaofeng Guo, Jianlong Huang, Nansong Li, Xueqing Hu, Rongde Ou, Wenzhe Liu, Bei Chen, Wen Zhang, Xiaofeng Xin, Bingcai Zhao, Zhenqi Chen. 396-398 [doi]
- 2 BLE Transceiver With Self IQ-Phase Correction Achieving 39dB Image Rejection and on-Chip Antenna Impedance TuningKenichi Shibata, Hiroaki Matsui, Hironori Asano, Yuichi Kusaka, Keisuke Ueda, Noriaki Matsuno, Hisayasu Sato. 398-400 [doi]
- A 266µW Bluetooth Low-Energy (BLE) Receiver Featuring an N-Path Passive Balun-LNA and a Pipeline Down-Mixing BB-Extraction Scheme Achieving 77dB SFDR and -3dBm OOB-B-1dBHaijun Shao, Pui-In Mak, Gengzhen Qi, Rui P. Martins. 400-402 [doi]
- A 110µW 2.5kb/s -103dBm-Sensitivity Dual-Chirp Modulated ULP Receiver Achieving -41dB SIRMilad Moosavifar, Jaeho Im, Trevor Odelberg, David D. Wentzloff. 402-404 [doi]
- An LPWAN Radio with a Reconfigurable Data/Duty-Cycled-Wake-Up ReceiverKeun-Mok Kim, Kyung-Sik Choi, Hyunki Jung, Byeonghun Yun, Subin Kim, Wonkab Oh, Eui-Soo Lee, Sujin Park, Eui-Rim Jeong, Jinho Ko, Sang-Gug Lee. 404-406 [doi]
- rd-Order VCO-Based ADC With Pseudo Virtual Ground Feedforward LinearizationCorentin Pochet, Drew A. Hall. 408-410 [doi]
- A 2.87μW 1kHz-BW 94.0dB-SNDR 2-0 MASH ADC Using FIA with Dynamic-Body-Biasing Assisted CLS TechniqueYaopeng Hu, YiBo Zhao, Wanyuan Qu, Le Ye, Menglian Zhao, Zhichao Tan. 410-412 [doi]
- 2 203.5µW 108.8dB DR DT Single-Loop DSM Audio ADC Using a Single-Ended Ring-Amplifier-Based Integrator in 180nm CMOSCalvin Yoji Lee, Un-Ku Moon. 412-414 [doi]
- A 5GS/s 360MHz-BW 68dB-DR Continuous-Time 1-1-1 Filtering MASH ΔΣ ADC in 40nm CMOSQilong Liu, Lucien J. Breems, Chenming Zhang, Shagun Bajoria, Muhammed Bolatkale, Robert Rutten, Georgi I. Radulov. 414-416 [doi]
- A 28nm 6GHz 2b Continuous-Time ΔΣ ADC with -101 dBc THD and 120MHz Bandwidth Using Digital DAC Error CorrectionMuhammed Bolatkale, Robert Rutten, Hans Brekelmans, Shagun Bajoria, Yihan Gao, Bernard Burdiek, Lucien J. Breems. 416-418 [doi]
- th-Order Noise-Shaping SAR with an FIA-Assisted EF-CRFF Structure and Noise-Mitigated Push-Pull Buffer-in-Loop TechniqueTzuhan Wang, Tian Xie, Zhe Liu, Shaolan Li. 418-420 [doi]
- Beyond-Classical Computing Using Superconducting Quantum ProcessorsJoseph C. Bardin. 422-424 [doi]
- Augmented Reality - The Next Frontier of Image Sensors and Compute SystemsChiao Liu, Song Chen, Tsung-Hsun Tsai, Barbara De Salvo, Jorge Gomez. 426-428 [doi]
- 3D V-Cache: the Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7nm x86-64 CPUJohn Wuu, Rahul Agarwal, Michael Ciraula, Carl Dietz, Brett Johnson, Dave Johnson, Russell Schreiber, Raja Swaminathan, Will Walker, Samuel Naffziger. 428-429 [doi]
- A Power-Efficient 24-to-71 GHz CMOS Phased-Array Receiver Utilizing Harmonic-Selection Technique Supporting 36dB Inter-Band Blocker Rejection for 5G NRJian Pang, Yi Zhang, Zheng Li, Minzhe Tang, Yijing Liao, Ashbir Aviat Fadila, Atsushi Shirane, Kenichi Okada. 434-436 [doi]
- A 24-to-30GHz 256-Element Dual-Polarized 5G Phased Array with Fast Beam-Switching Support for >30, 000 BeamsBodhisatwa Sadhu, Arun Paidimarri, Wooram Lee, Mark Yeck, Caglar Ozdag, Yujiro Tojo, Jean-Olivier Plouchart, Xiaoxiong Gu, Yusuke Uemichi, Sudipto Chakraborty, Yo Yamaguchi, Ning Guan, Alberto Valdes-Garcia. 436-438 [doi]
- A Hybrid Coupler-First 5GHz Noise-Cancelling Dual-Mode Receiver with +10dBm in-Band IIP3 in Current-Mode and 1.7dB NF in Voltage-ModeKaituo Yang, Chirn Chye Boon, Zhe Liu, Jiaming Piao, Ting Guo, Yangtao Dong, Chenyang Li, Ao Zhou, Zhijie Yang, Xiaoying Wang, Yufeng Liu. 438-440 [doi]
- A Single-Path Digital-IF Receiver Supporting Inter/Intra 5-CA with a Single Integer LO-PLL in 14nm CMOS FinFETBarosaim Sung, Hyun-Gi Seok, Jaekwon Kim, Jaehoon Lee, Taejin Jang, Ilhoon Jang, Youngmin Kim, Anna Yu, Jong-Hyun Jang, Jiyoung Lee, Jeongyeol Bae, Euiyoung Park, Sung-Jun Lee, Seokwon Lee, Joohan Kim, Beomkon Kim, Yong Lim, Seunghyun Oh, Jongwoo Lee, Thomas Byunghak Cho, Inyup Kang. 440-442 [doi]
- A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout OptimizationMyeong-Jae Park, Ho Sung Cho, Tae Sik Yun, Sangjin Byeon, Young Jun Koo, Sang-Sic Yoon, Dong Uk Lee, Seokwoo Choi, Ji-Hwan Park, Jinhyung Lee, Kyungjun Cho, Junil Moon, Byung Kuk Yoon, Young-Jun Park, Sangmuk Oh, Chang Kwon Lee, Tae-Kyun Kim, Seong-Hee Lee, Hyun Woo Kim, Yucheon Ju, Seung-Kyun Lim, Seung Geun Baek, Kyo Yun Lee, Sang-Hun Lee, Woo Sung We, Seungchan Kim, Yongseok Choi, Seong-Hak Lee, Seung-Min Yang, Gunho Lee, In-Keun Kim, Younghyun Jeon, Jae Hyung Park, Jong-Chan Yun, Chanhee Park, Sun-Yeol Kim, Sungjin Kim, Dong Yeol Lee, Su-Hyun Oh, Taejin Hwang, Junghyun Shin, Yunho Lee, Hyunsik Kim, Jaeseung Lee, Youngdo Hur, Sangkwon Lee, Jieun Jang, Junhyun Chun, Joohwan Cho. 444-446 [doi]
- A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-BusDaewoong Lee, Hye-Jung Kwon, Daehyun Kwon, Jaehyeok Baek, Chulhee Cho, Sanghoon Kim, Donggun An, Chulsoon Chang, Unhak Lim, Jiyeon Im, Wonju Sung, Hye-Ran Kim, Sun Young Park, HyoungJoo Kim, Ho-Seok Seol, Juhwan Kim, Junabum Shin, Kil-Youna Kang, Yong Hun Kim, Sooyoung Kim, Wansoo Park, Seok-Jung Kim, Chanyong Lee, SeungSeob Lee, Taehoon Park, Chi Sung Oh, Hyodong Ban, Hyungjong Ko, Hoyoung Song, Tae-young Oh, Sangjoon Hwang, Kyung Suk Oh, Jung Hwan Choi, Jooyoung Lee. 446-448 [doi]
- A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM ProcessDae-Hyun Kim, Byungkyu Song, Hyun-a Ahn, Woongjoon Ko, Sung-Geun Do, Seokjin Cho, Kihan Kim, Seung-Hoon Oh, Hye-Yoon Joo, Geuntae Park, Jin-Hun Jang, Yong Hun Kim, Donghun Lee, Jaehoon Jung, Yongmin Kwon, Youngjae Kim, Jaewoo Jung, Seongil O, Seoulmin Lee, Jaeseong Lim, Junho Son, Jisu Min, Haebin Do, Jaejun Yoon, Isak Hwang, Jinsol Park, Hong Shim, Seryeong Yoon, Dongyeong Choi, Jihoon Lee, Soohan Woo, Eunki Hong, Junha Choi, Jae-Sung Kim, Sangkeun Han, Jong-Min Bang, Bokgue Park, Jang-Hoo Kim, Seouk-Kyu Choi, Gong-Heum Han, Yoo-Chang Sung, Wonil Bae, Jeong-Don Lim, Seungjae Lee, Changsik Yoo, Sang Joon Hwang, Jooyoung Lee. 448-450 [doi]
- 2Single-Ended Inverter-based 4-tap Addition-Only Feed-Forward Equalization Transmitter with Improved Robustness to Coefficient Errors in 28nm CMOSChangjae Moon, Jaeyoung Seo, Myungguk Lee, Iksu Jang, Byungsub Kim. 450-452 [doi]
- A 78.8fJ/b/mm 12.0Gb/s/Wire Capacitively Driven On-Chip Link Over 5.6mm with an FFE-Combined Ground-Forcing Biasing Technique for DRAM Global Bus Line in 65nm CMOSSangyoon Lee, Jaekwang Yun, Suhwan Kim. 454-456 [doi]
- A 28nm 15.59µJ/Token Full-Digital Bitline-Transpose CIM-Based Sparse Transformer Accelerator with Pipeline/Parallel Reconfigurable ModesFengbin Tu, Zihan Wu, Yiqi Wang, Ling Liang, Liu Liu, Yufei Ding, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin. 466-468 [doi]
- A 130V Triboelectric Energy-Harvesting Interface in .18µm BCD with Scalable Multi-Chip-Stacked Bias-Flip and Daisy-Chained Synchronous Signaling TechniqueJiho Lee, Sang-Han Lee, Gyeong-Gu Kang, Jae-Hyun Kim, Gyu-Hyeong Cho, Hyun-Sik Kim. 474-476 [doi]
- % Efficiency in Direct Charging ModeSung-Woo Lee, Taejin Jeong, Yonghwan Cho, Jeongdu Yoo, Sung-Kyu Cho, Minkyu Kwon, Dae-Woong Cho, Sang-Hee Kang, Jung-Wook Heo, Hyoung-Seok Oh, Sung-Ung Kwak. 476-478 [doi]
- A 0.76V Vin Triode Region 4A Analog LDO with Distributed Gain Enhancement and Dynamic Load-Current Tracking in Intel 4 CMOS Featuring Active Feedforward Ripple Shaping and On-Chip Power Noise AnalyzerXiaosen Liu, Harish Krishnamurthy, Renzhi Liu, Krishnan Ravichandran, Zakir Ahmed, Nachiket V. Desai, Nicolas Butzen, James W. Tschanz, Vivek De. 478-480 [doi]
- A -117dBc THD (-132dBc HD3) and 126dB DR Audio Decoder with Code-Change-Insensitive RT-DEM Algorithm and Circuit Technique for Relaxing Velocity Saturation Effect of Poly ResistorsShon-Hang Wen, Chuan-Hung Hsiao, Shih-Hsiung Chien, Ya-Chi Chen, Kuan-Hung Chen, Kuan-Dar Chen. 482-484 [doi]
- A 121dB DR, 0.0017% THD+N, 8× Jitter-Effect Reduction Digital-Input Class-D Audio Amplifier with Supply-Voltage-Scaling Volume Control and Series-Connected DSMWei-Hao Sun, Shih-Hsiung Chien, Tai-Haur Kuo. 486-488 [doi]
- BatDrone: A 9.83M-focal-points/s 7.76µs-Latency Ultrasound Imaging System with On-Chip Per-Voxel RX Beamfocusing for 7m-Range Drone ApplicationsLiuhao Wu, Jiaqi Guo, Rucheng Jiang, Yande Peng, Han Wu, Jiamin Li, Yilong Dong, Miaolin Zhang, Zhuoyue Li, Kian Ann Ng, Chne Wuen Tsai, Lian Zhang, Longyang Lin, Liwei Lin, Jerald Yoo. 492-494 [doi]
- A Pitch-Matched ASIC with Integrated 65V TX and Shared Hybrid Beamforming ADC for Catheter-Based High-Frame-Rate 3D Ultrasound ProbesYannick Hopf, Boudewine W. Ossenkoppele, Mehdi Soozande, Emile Noothout, Zu-yao Chang, Chao Chen 0019, Hendrik J. Vos, Hans G. Bosch, Martin D. Verweij, Nico de Jong, Michiel A. P. Pertijs. 494-496 [doi]
- A 1.2mW/channel 100µm-Pitch-Matched Transceiver ASIC with Boxcar-Integration-Based RX Micro-Beamformer for High-Resolution 3D Ultrasound ImagingPeng Guo, Fabian Fool, Emile Noothout, Zu-Vao Chang, Hendrik J. Vos, Johan G. Bosch, Martin D. Verweij, Nico de Jonq, Michiel A. P. Pertijs. 496-498 [doi]
- An Electronically Tunable Multi-Frequency Air-Coupled CMUT Receiver Array with sub-100µPa Minimum Detectable Pressure Achieving a 28kb/s Wireless Uplink Across a Water-Air InterfaceAjay Singhvi, Aidan Fitzpatrick, Amin Arbabian. 498-500 [doi]
- A Multimode 157μW 4-Channel 80dBA-SNDR Speech-Recognition Frontend With Self-DOA Correction Adaptive BeamformerTaewook Kang, Seungjong Lee, Seungheun Song, Mohammad R. Haghighat, Michael P. Flynn. 500-502 [doi]
- A 1.05A/m Minimum Magnetic Field Strength Single-Chip Fully Integrated Biometric Smart Card SoC Achieving 1014.7ms Transaction Time with Anti-Spoofing Fingerprint AuthenticationJi-Soo Chang, Eunsang Jang, Youngkil Choi, Moonkyu Song, Sanghyo Lee, Gi-Jin Kang, Junho Kim, Shin-Wuk Kang, Uijong Song, Chang-Yeon Cho, Junseo Lee, Kyungduck Seo, Seongwook Song, Sung-Ung Kwak. 504-506 [doi]
- DSPU: A 281.6mW Real-Time Depth Signal Processing Unit for Deep Learning-Based Dense RGB-D Data Acquisition with Depth Fusion and 3D Bounding Box Extraction in Mobile PlatformsDongseok Im, Gwangtae Park, Zhiyong Li, Junha Ryu, Sanghoon Kang, Donghyeon Han, Jinsu Lee, Hoi-Jun Yoo. 510-512 [doi]
- A 28nm 48KOPS 3.4µJ/Op Agile Crypto-Processor for Post-Quantum Cryptography on Multi-Mathematical ProblemsYihong Zhu, Wenping Zhu, Min Zhu, Chongyang Li, Chenchen Deng, Chen Chen, Shuying Yin, Shouyi Yin, Shaojun Wei, Leibo Liu. 514-516 [doi]
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