A 188fsrms-Jitter and -243d8-FoMjitter 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector - researchr publication

researchr

You are not signed in
Sign in
Sign up

Chanwoong Hwang, Hangi Park, Taeho Seong, Jaehyouk Choi. A 188fsrms-Jitter and -243d8-FoMjitter 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector. In IEEE International Solid-State Circuits Conference, ISSCC 2022, San Francisco, CA, USA, February 20-26, 2022. pages 378-380, IEEE, 2022. [doi]

Abstract is missing.

runs on WebDSL