A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus

Daewoong Lee, Hye-Jung Kwon, Daehyun Kwon, Jaehyeok Baek, Chulhee Cho, Sanghoon Kim, Donggun An, Chulsoon Chang, Unhak Lim, Jiyeon Im, Wonju Sung, Hye-Ran Kim, Sun Young Park, HyoungJoo Kim, Ho-Seok Seol, Juhwan Kim, Junabum Shin, Kil-Youna Kang, Yong Hun Kim, Sooyoung Kim, Wansoo Park, Seok-Jung Kim, Chanyong Lee, SeungSeob Lee, Taehoon Park, Chi Sung Oh, Hyodong Ban, Hyungjong Ko, Hoyoung Song, Tae-young Oh, Sangjoon Hwang, Kyung Suk Oh, Jung Hwan Choi, Jooyoung Lee. A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus. In IEEE International Solid-State Circuits Conference, ISSCC 2022, San Francisco, CA, USA, February 20-26, 2022. pages 446-448, IEEE, 2022. [doi]

Abstract

Abstract is missing.