D. Zhou - researchr alias

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2023

2022

2019

TCAD Simulation on FinFET n-type Power Device HCI Reliability ImprovementB. Zhu, E. M. Bazizi, J. H. M. Tng, Z. Li, E. K. Banghart, M. K. Hassan, Y. Hu, D. Zhou, D. Choi, L. Qin, X. Wan. irps 2019: 1-4 [doi]

2018

Reliability assessment of power conditioner considering maintenance in a PEM fuel cell systemS. Bahrebar, D. Zhou, S. Rastayesh, H. Wang, Frede Blaabjerg. mr, 88:1177-1182, 2018. [doi]

Mission profile resolution impacts on the thermal stress and reliability of power devices in PV invertersA. Sangwongwanich, D. Zhou, Elizaveta Liivik, Frede Blaabjerg. mr, 88:1003-1007, 2018. [doi]

2017

Fundamental-frequency and load-varying thermal cycles effects on lifetime estimation of DFIG power converterG. Zhang, D. Zhou, J. Yang, Frede Blaabjerg. mr, 76:549-555, 2017. [doi]

2015

2014

2013

Determination of the optimal trade credit policy: a supplier-Stackelberg modelY.-W. Zhou, D. Zhou. jors, 64(7):1030-1048, 2013. [doi]

2012

Two Miniaturized Printed Dual-Band Spiral Antenna Designs for Satellite Communication SystemsMohammed S. Bin-Melha, Chan H. See, Raed A. Abd-Alhameed, M. S. Alkambashi Alkambashi, D. Zhou, Steve M. R. Jones, Peter S. Excell. psats 2013: 81-86 [doi]

2011

Erratum to An Extended Periodic Imperfect Preventive Maintenance Model With Age-Dependent Failure Type [Jun 09 397-405]Shey-Huei Sheu, Chin-Chih Chang, X. Lu, D. Zhou. tr, 60(2):515, 2011. [doi]

2010

New compact dual polarised dipole antenna for MIMO communicationsM. Usman, R. A. Abd-Alhameed, Y. A. S. Dama, Peter S. Excell, D. Zhou, B. Ibrahim, E. Almahdi Elkhazmi. wsa 2010: 326-330 [doi]

2005

Design and Development of a Low-Cost Test-Bed for Undergraduate Education in UAVsDongwon Jung, E. J. Levy, D. Zhou, R. Fink, J. Moshe, A. Earl, Panagiotis Tsiotras. cdc 2005: 2739-2744 [doi]

2004

Cluster Computing on the Fly: resource discovery in a cycle sharing peer-to-peer systemD. Zhou, V. Lo. ccgrid 2004: 66-73 [doi]

2001

Automatic clock tree design with IPs in the systemW. Li, D. Zhou, H. Kim, X. Zeng. iscas 2001: 387-390 [doi]

Design of GHz VLSI clock distribution circuitX. Zeng, D. Zhou. iscas 2001: 391-394 [doi]

An efficient balanced truncation realization algorithm for interconnect model order reductionD. Zhou, Wei Li, W. Cai, N. Guo. iscas 2001: 383-386 [doi]

1999

A constraint-based placement refinement method for CMOS analog cell layoutX. Zeng, J. Guan, W. Q. Zhao, P. S. Tang, D. Zhou. iscas 1999: 408-411 [doi]

Buffer insertion for clock delay and skew minimizationX. Zeng, D. Zhou, Wei Li. ispd 1999: 36-41 [doi]

1997

Minimization of chip size and power consumption of high-speed VLSI buffersD. Zhou, X. Y. Liu. ispd 1997: 186-191 [doi]

1995

A fast wavelet collocation method for high-speed VLSI circuit simulationD. Zhou, N. Chen, W. Cai. iccad 1995: 115-122 [doi]

1993

On the Manhattan and knock-knee Routing ModelsD. Zhou, Franco P. Preparata. In Majid Sarrafzadeh, D. T. Lee, editors, Algorithmic Aspects of VLSI Layout. Volume 2 of Lecture Notes Series on Computing, pages 245-264, World Scientific, 1993. [doi]

1988

Interconnection delay in very high-speed VLSID. Zhou, Franco P. Preparata, S. M. Kang. iccd 1988: 52-55 [doi]

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