Abstract is missing.
- Issues in Timing Driven LayoutMalgorzata Marek-Sadowska. 1-24 [doi]
- Binary formulations for Placement and Routing ProblemsS. M. Kang, M. Sriram. 25-68 [doi]
- A Survey of Parallel Algorithms for VLSI cell PlacementPrithviraj Banerjee. 69-131 [doi]
- Approximate solutions for Graph and Hypergraph PartitioningFillia Makedon, Spyros Tragoudas. 133-166 [doi]
- Integer Program formulations of Global Routing and Placement ProblemsThomas Lengauer, Martin Lügering. 167-197 [doi]
- Circuit Partitioning Algorithms based on Geometry ModelTetsuo Asano, Takeshi Tokuyama. 199-212 [doi]
- The three-dimensional channel Routing ProblemMartin L. Brady, Donna J. Brown, Patrick J. McGuiness. 213-244 [doi]
- On the Manhattan and knock-knee Routing ModelsD. Zhou, Franco P. Preparata. 245-264 [doi]
- Switch-Box Routing under the two-Overlap wiring ModelTeofilo F. Gonzalez, Shashishekhar Kurki-Gowdara, Si-Qing Zheng. 265-308 [doi]
- A note on the Complexity of Stockmeyer's floorplan Optimization TechniqueTing-Chi Wang, D. F. Wong. 309-320 [doi]
- An Algorithm to Eliminate All Complex Triangles in a Maximal Planar Graph for Use in VLSI floorplanShuji Tsukiyama, Keiichi Koike, Isao Shirakawa. 321-335 [doi]
- Constrained via Minimization and Signed Hypergraph PartitioningChuan-Jin Shi. 337-356 [doi]
- The Virtual Dimensions of a Straight Line Embedding of a plane GraphToshihiko Takahashi, Yoji Kajitani. 357-363 [doi]
- Routing around two Rectangles to minimize the Layout AreaTeofilo F. Gonzalez, Sing-Ling Lee. 365-397 [doi]