Table of Contents

• The deep sub-micron signal integrity challengeDesmond Kirkpatrick. 4-7 [doi]
• A methodology to analyze power, voltage drop and their effects on clock skew/delay in early stages of designMasato Iwabuchi, Noboru Sakamoto, Yasushi Sekine, Takashi Omachi. 9-15 [doi]
• EMI-noise analysis under ASIC design environmentSachio Hayashi, Masaaki Yamada. 16-21 [doi]
• An efficient sequential quadratic programming formulation of optimal wire spacing for cross-talk noise avoidance routingPaul B. Morton, Wayne Wei-Ming Dai. 22-28 [doi]
• Post-routing timing optimization with routing characterizationChieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai. 30-35 [doi]
• Buffer insertion for clock delay and skew minimizationX. Zeng, D. Zhou, Wei Li. 36-41 [doi]
• Interconnect coupling noise in CMOS VLSI circuitsKevin T. Tang, Eby G. Friedman. 48-53 [doi]
• SRC physical design top ten problemJeff Parkhurst, Naveed A. Sherwani, Sury Maturi, Dana Ahrams, Eli Chiprout. 55-58 [doi]
• Towards synthetic benchmark circuits for evaluating timing-driven CAD toolsDirk Stroobandt, Peter Verplaetse, Jan Van Campenhout. 60-66 [doi]
• Generation of very large circuits to benchmark the partitioning of FPGAJoachim Pistorius, Edmée Legai, Michel Minoux. 67-73 [doi]
• Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesisMichael A. Riepe, Karem A. Sakallah. 74-81 [doi]
• Partitioning by iterative deletionPatrick H. Madden. 83-89 [doi]
• Optimal partitioners and end-case placers for standard-cell layoutAndrew E. Caldwell, Andrew B. Kahng, Igor L. Markov. 90-96 [doi]
• Slicing floorplans with range constraintFung Yu Young, D. F. Wong. 97-102 [doi]
• Arbitrary convex and concave rectilinear block packing using sequence-pairKunihiro Fujiyoshi, Hiroshi Murata. 103-110 [doi]
• Subwavelength optical lithography: challenges and impact on physical designAndrew B. Kahng, Y. C. Pati. 112-119 [doi]
• Optimal phase conflict removal for layout of dark field alternating phase shifting masksPiotr Berman, Andrew B. Kahng, Devendra Vidhani, Huijuan Wang, Alexander Zelikovsky. 121-126 [doi]
• Gate sizing with controlled displacementWei Chen, Cheng-Ta Hsieh, Massoud Pedram. 127-132 [doi]
• Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE modelJiang Hu, Sachin S. Sapatnekar. 133-138 [doi]
• Efficient solution of systems of orientation constraintsJoseph L. Ganley. 140-144 [doi]
• On the behavior of congestion minimization during placementMaogang Wang, Majid Sarrafzadeh. 145-150 [doi]
• Partitioning with terminals: a new problem and new benchmarksCharles J. Alpert, Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov. 151-157 [doi]
• Transistor level placement for full custom datapath cell designDurgam Vahia, Maciej J. Ciesielski. 158-163 [doi]
• Circuit clustering using graph coloringAmit Singh, Malgorzata Marek-Sadowska. 164-169 [doi]
• Interconnect thermal modeling for determining design limits on current densityDanqing Chen, Erhong Li, Elyse Rosenbaum, Sung-Mo Kang. 172-178 [doi]
• Standard cell placement for even on-chip thermal distributionChing-Han Tsai, Sung-Mo Kang. 179-184 [doi]
• A method of measuring nets routability for MCM s general area routing problemsKusnadi, Jo Dale Carothers. 186-192 [doi]
• Getting to the bottom of deep submicron II: a global wiring paradigmDennis Sylvester, Kurt Keutzer. 193-200 [doi]
• Crosstalk constrained global route embeddingPhiroze N. Parakh, Richard B. Brown. 201-206 [doi]
• Timing driven maze routingSung-Woo Hur, Ashok Jagannathan, John Lillis. 208-213 [doi]
• VIA design rule consideration in multi-layer maze routing algorithmsJason Cong, Jie Fang, Kei-Yong Khoo. 214-220 [doi]