Abstract is missing.
- Novel Gyrotron Beam Annealing Method for Mg-Implanted Bulk GaNK. Hogan, S. Tozier, E. Rocco, I. Mahaboob, V. Meyers, B. McEwen, F. Shahedipour-Sandvik, R. Tompkins, M. Derenge, Kenneth Jones, M. Shevelev, V. Sklyar, A. Lang, J. Hart, M. Taheri, M. Reshchikov. 1-6 [doi]
- A Comparison of Environmental Stressing Data and Simulation at the Corner of a Test Chip in a FC-BGA PackageSandeep Mallampati, Zaeem Baig, Scott Pozder, Eng Chye Chua. 1-4 [doi]
- HCI Improvement on 14nm FinFET IO Device by Optimization of 3D Junction ProfileXinggon Wan, Baofu Zhu, Meera Mohan, Keija Wu, Dongil Choi, Arfa Gondal. 1-4 [doi]
- Positive Bias Instability in ZnO TFTs with Al2O3 Gate DielectricPavel Bolshakov, Rodolfo A. Rodriguez-Davila, Manuel Quevedo-Lopez, Chadwin D. Young. 1-5 [doi]
- Alternating Temperature Stress and Deduction of Effective Stress Levels from Mission Profiles for Semiconductor ReliabilityA. Hirler, A. Alsioufy, J. Biba, T. Lehndorff, D. Lipp, H. Lochner, M. Siddabathula, S. Simon, T. Sulima, M. Wiatr, Walter Hansch. 1-4 [doi]
- Dielectric Breakdown in 2D Layered Hexagonal Boron Nitride - The Knowns and the UnknownsKin Leong Pey, A. Ranjan, Nagarajan Raghavan, Kalya Shubhakar, Sean J. O'Shea. 1-12 [doi]
- Accelerated Device Degradation of High-Speed Ge Waveguide PhotodetectorsAlicja Lesniewska, S. A. Srinivasan, Joris Van Campenhout, B. J. O'Sullivan, Kris Croes. 1-7 [doi]
- An Analytical Transient Joule Heating Model for an Interconnect in a Modern IC: Material Selection (Cu, Co, Ru) and Cooling StrategiesWoojin Ahn, Yen-Pu Chen, Muhammad Ashraful Alam. 1-6 [doi]
- Flight Safety Certification Implications for Complex Multi-Core Processor Based Avionics SystemsJyotika Athavale, Riccardo Mariani, Michael Paulitsch. 1-6 [doi]
- Comprehensive Methodology for Multiple Spots Competing Progressive Breakdown for BEOL/FEOL ApplicationsErnest Y. Wu, Baozhen Li, James H. Stathis, Andrew Kim. 1-8 [doi]
- Low-Side GaN Power Device Dynamic Ron Characteristics Under Different Substrate BiasesWen Yang, Jiann-shiun Yuan, Balakrishnan Krishnan, Patrick Shea. 1-7 [doi]
- Characterization of Critical Peak Current and General Model of Interconnect Systems Under Short Pulse-Width ConditionsM. H. Lin, W. S. Chou, Y.-T. Yang, A. S. Oates. 1-7 [doi]
- Reliability Challenges with Materials for Analog ComputingEduard A. Cartier, Wanki Kim, Nanbo Gong, Tayfun Gokmen, Martin M. Frank, Douglas M. Bishop, Youngseok Kim, Seyoung Kim, Takashi Ando, Ernest Y. Wu, Praneet Adusumilli, John Rozen, Paul M. Solomon, Wilfried Haensch, Matthew J. BrightSky, Abu Sebastian, Geoffrey W. Burr, Vijay Narayanan. 1-10 [doi]
- Impact of Sidewall Etching on the Dynamic Performance of GaN-on-Si E-Mode TransistorsAlaleh Tajalli, E. Canato, A. Nardo, Matteo Meneghini, Arno Stockman, Peter Moens, Enrico Zanoni, Gaudenzio Meneghesso. 1-6 [doi]
- Novel Oxide Top-Off Process Enabling Reliable PC-CA TDDB on IO Devices with Self Aligned ContactTian Shen, Abu Naser Zainuddin, Purushothaman Srinivasan, Zakariae Chbili, Kai Zhao, Patrick Justison. 1-5 [doi]
- Neutron Beam Attenuation Through Semiconductor Devices During SEU TestingS. A. Wender, J. M. O'Donnell, L. Zavorka, B. L. Bhuva. 1-4 [doi]
- Impact of NBTI on Increasing the Susceptibility of FinFET to RadiationFrank Sill Torres, Hussam Amrouch, Jörg Henkel, Rolf Drechsler. 1-6 [doi]
- Operational Workload Impact on Robust Solid-State Storage Analyzed with Interpretable Machine LearningJay Sarkar, Cory Peterson. 1-8 [doi]
- Modeling the Effect of Random Dopants on Hot-Carrier Degradation in FinFETsAlexander Makarov, Ben Kaczer, Philippe Roussel, Adrian Chasin, A. Grill, Michiel Vandemaele, Geert Hellings, A.-M. El-Sayed, Tibor Grasser, Dimitri Linten, Stanislav Tyaginov. 1-7 [doi]
- A Novel Constant E-Field Methodology for Intrinsic TDDB Lifetime ProjectionA. S. Teng, C.-W. Lin, M. N. Chang, Aaron Wang, Ryan Lu. 1-7 [doi]
- Scaling Behaviour of State-to-State Coupling During Hole Trapping at Si/SiO2Xiaolei Ma, Xiangwei Jiang, Jiezhi Chen, Liwei Wang 0003, Yunfei En. 1-4 [doi]
- Electromigration Early Failures for Cu Pillar Interconnections with an ENEPIG Pad Finish and its SuppressionHideaki Tsuchiya, Naohito Suzumura, Ryuji Shibata, Hideki Aono, Makoto Ogasawara, Toshihiko Akiba, Kenji Sakata, Kazuyuki Nakagawa, Takuo Funaya. 1-6 [doi]
- UV-Assisted Probing of Deep-Level Interface Traps in GaN MISHEMTs and Their Role in Threshold Voltage & Gate Leakage InstabilitiesSayak Dutta Gupta, Vipin Joshi, Bhawani Shankar, Swati Shikha, Srinivasan Raghavan, Mayank Shrivastava. 1-5 [doi]
- Comprehensive Study for OFF-State Hot Carrier Degrdation of Scaled nMOSFETs in DRAMNam-Hyun Lee, Jongkyun Kim, Donghee Son, Kangjun Kim, Jung-Eun Seok. 1-4 [doi]
- Experimental Implementation of 8.9Kgate Stress Monitor in 28nm MCU Along with Safety Software Library for IoT Device MaintenanceKan Takeuchi, Masaki Shimada, Shinya Konishi, Daisuke Oshida, Naoya Ota, Takashi Yasumasu, Koji Shibutani, Tomohiro Iwashita, Tetsuya Kokubun, Fumio Tsuchiya. 1-7 [doi]
- Exploration of the Impact of Physical Integration Schemes on Soft Errors in 3D ICs Using Monte Carlo SimulationM. L. Breeding, R. A. Reed, K. M. Warren, M. L. Alles. 1-7 [doi]
- Process Variation of Pixel Definition and Effects of Flexible OLED Luminance DegradationJongwon Lee, Sangkil Kim, Yoonsuk Choi, Jongwoo Park. 1-6 [doi]
- Spatio-Temporal Defect Generation Process in Irradiated HfO2 MOS Stacks: Correlated Versus Uncorrelated MechanismsFernando Leonel Aguirre, Andrea Padovani, Alok Ranjan, Nagarajan Raghavan, Nahuel Vega, Nahuel Muller, Sebastián Matías Pazos, Mario Debray, Joel Molina Reyes, Kin Leong Pey, Felix Palumbo. 1-8 [doi]
- Understanding and Variability of Lateral Charge Migration in 3D CT-NAND Flash with and Without Band-Gap Engineered BarriersAndrea Padovani, Milan Pesic, Mondol Anik Kumar, Pieter Blomme, Alexandre Subirats, Senthil Vadakupudhupalayam, Zunaid Baten, Luca Larcher. 1-8 [doi]
- Time-Dependent Dielectric Breakdown Under AC Stress in GaN MIS-HEMTsEthan S. Lee, Luis Hurtado, Jungwoo Joh, Srikanth Krishnan, Sameer Pendharkar, Jesús A. del Alamo. 1-5 [doi]
- Surrogate Model Assisted Design of Silicon Anode Considering Lithiation Induced StressesZhuoyuan Zheng, Bo Chen, Yashraj Gurumukhi, John Cook, Mehmet N. Ates, Nenad Miljkovic, Paul V. Braun, Pingfeng Wang. 1-6 [doi]
- TCAD Simulation on FinFET n-type Power Device HCI Reliability ImprovementB. Zhu, E. M. Bazizi, J. H. M. Tng, Z. Li, E. K. Banghart, M. K. Hassan, Y. Hu, D. Zhou, D. Choi, L. Qin, X. Wan. 1-4 [doi]
- Novel RC-Clamp Design for High Supply VoltageYuh-Yue Chen, Tsyr-Shyang Liou, Shyh-Chyi Wong. 1-6 [doi]
- Impact of Mechanical Stress on the Electrical Performance of 3D NANDA. Kruv, A. Arreghini, M. Gonzalez, D. Verreck, G. Van den bosch, I. De Wolf, A. Furnemont. 1-5 [doi]
- From Device Aging Physics to Automated Circuit Reliability Sign OffChristian Schlünder, Katja Waschneck, Peter Rotter, Susanne Lachenmann, Hans Reisinger, Franz Ungar, Georg Georgakos. 1-12 [doi]
- High Resolution Observation of Subsurface Defects at SiO2/4H-SiC Interfaces by Local Deep Level Transient Spectroscopy Based on Time-Resolved Scanning Nonlinear Dielectric MicroscopyYuji Yamagishi, Yasuo Cho. 1-4 [doi]
- Tolerance of Deep Neural Network Against the Bit Error Rate of NAND Flash MemoryMehedi Hasan, Biswajit Ray. 1-4 [doi]
- Transformation of Ramped Current Stress VBDto Constant Voltage Stress TDDB TBDAndrew Kim, Ernest Y. Wu, Baozhen Li, Barry P. Linder. 1-5 [doi]
- Alpha Particle Soft-Error Rates for D-FF Designs in 16-Nm and 7-Nm Bulk FinFET TechnologiesJ. Cao, L. Xu, Bharat L. Bhuva, S.-J. Wen, R. Wong, Balaji Narasimham, Lloyd W. Massengill. 1-5 [doi]
- $\mu s$-Range Evaluation of Threshold Voltage Instabilities of GaN-on-Si HEMTs with p-GaN GateE. Canato, F. Masin, Matteo Borga, Enrico Zanoni, Matteo Meneghini, Gaudenzio Meneghesso, Arno Stockman, A. Banerjee, Peter Moens. 1-6 [doi]
- Characterization and Modeling of the Transient Safe Operating Area in LDMOS TransistorsHang Li, Kalpathy B. Sundaram, Yuanzhong (Paul) Zhou, Javier A. Salcedo, Jean-Jacques Hajjar. 1-5 [doi]
- Process-Induced Anomalous Current Transport in Graphene/InA1N/GaN Heterostructured DiodesPeter F. Satterthwaite, Ananth Saran Yalamarthy, Sam Vaziri, Miguel Munoz-Rojo, Eric Pop, Debbie G. Senesky. 1-6 [doi]
- New Insights into the Imprint Effect in FE-HfO2 and its RecoveryY. Higashi, Karine Florent, A. Subirats, Ben Kaczer, Luca Di Piazza, Sergiu Clima, N. Ronchi, S. R. C. McMitchell, K. Banerjee, Umberto Celano, M. Suzuki, Dimitri Linten, Jan Van Houdt. 1-7 [doi]
- Reliability Testing of SiC MOS Devices at 500°CA. C. Ahyi, S. Dhar, Zeynep Dilli, Akin Akturk, Neil Goldsman, A. Ghanbari. 1-4 [doi]
- Modeling of Apparent Activation Energy and Lifetime Estimation for Retention of 3D SGVC MemoryWei-Hao Hsiao, Nian-Jia Wang, Ming-Yi Lee, Li-Kuang Kuo, Ding-Jhang Lin, Yen-Hai Chao, Chih-Yuan Lu. 1-5 [doi]
- Tristate Resistive Switching in Heterogenous Van Der Waals Dielectric StructuresKaichen Zhu, Xianhu Liang, Bin Yuan, Marco A. Villena, Chao Wen, Tao Wang, Shaochuan Chen, Mario Lanza, Fei Hui, Yuanyuan Shi. 1-6 [doi]
- Novel Cumulative Degradation Approach to Predict Components Failure RatesGeorge Thiel, Flavio Griggio. 1-7 [doi]
- Analysis of Random Telegraph Noise (RTN) at Near-Threshold Operation by Measuring 154k Ring OscillatorsA. K. M. Mahfuzul Islam, Ryota Shimizu, Hidetoshi Onodera. 1-6 [doi]
- Verification of Copper Stress Migration Under Low Temperature Long Time StressHideya Matsuyama, Takashi Suzuki, Motoki Shiozu, Hideo Ehara, Takeshi Soeda, Hirokazu Hosoi, Masao Oshima, Kikuo Yamabe. 1-5 [doi]
- CDM-Time Domain Turn-on Transient of ESD Diodes in Bulk FinFET and GAA NW TechnologiesShih-Hung Chen, Dimitri Linten, Geert Hellings, Marco Simicic, Ben Kaczer, Thomas Chiarella, Hans Mertens, Jérôme Mitard, Anda Mocuta, N. Horiguchi. 1-7 [doi]
- Reliability Issues in Analog ReRAM Based Neural-Network ProcessorRyutaro Yasuhara, Takashi Ono, Reiji Mochida, Shunsaku Muraoka, Kazuyuki Kouno, Koji Katayama, Yuriko Hayata, Masayoshi Nakayama, Hitoshi Suwa, Yukio Hayakawa, Takumi Mikawa, Yasushi Gohou, Shinichi Yoneda. 1-5 [doi]
- Physical Model for ESD Human Body Model to Transmission Line PulseJian-Hsing Lee, Natarajan Mahadeva Iyer, Timothy J. Maloney. 1-7 [doi]
- Reliability of an Al2O3/SiO2MIM Capacitor for 180nm (3.3V) TechnologyJeff Gambino, Derryl D. J. Allman, Gavin D. R. Hall, D. Price, L. Sheng, R. Takada, Y. Kanuma. 1-5 [doi]
- An Accurate Device-Level Simulation Method to Estimate Cross Sections of Single Event Upsets by Silicon Thickness in Raised LayerKentaro Kojima, Kodai Yamada, Jun Furuta, Kazutoshi Kobayashi. 1-5 [doi]
- Understanding EM-Degradation Mechanisms in Metal Heaters Used for Si Photonics ApplicationsKris Croes, Veerle Simons, Sofie Beyne, Vladimir Cherman, Herman Oprins, Michele Stucchi, Ph. Absil, A. Glabman, Eric Wilcox. 1-4 [doi]
- Cycling Induced Trap Generation and Recovery Near the Top Select Gate Transistor in 3D NANDXingqi Zou, Liang Yan, Lei Jin, Da Li, Feng Xu, Di Ai, An Zhang, Hongtao Liu, Ming Wang, Wei Li, Yali Song, Huazheng Wei, Yi Chen, Chunlong Li, Zongliang Huo. 1-5 [doi]
- Study of Local BTI Variation and its Impact on Logic Circuit and SRAM in 7 nm Fin-FET ProcessMitsuhiko Igarashi, Yuuki Uchida, Yoshio Takazawa, Makoto Yabuuchi, Yasumasa Tsukamoto, Koji Shibutani. 1-6 [doi]
- Evaluation of Single Event Effects in SRAM and RRAM Based Neuromorphic Computing System for InferenceZhilu Ye, Rui Liu 0005, Hugh Barnaby, Shimeng Yu. 1-4 [doi]
- BEOL Process Development Using Fast Power Cycling on Test StructuresMatt Ring, Johan De Greve, Bill Cowell, Darren Moore, Jeff Gambino. 1-6 [doi]
- Switching Variability Factors in Compliance-Free Metal Oxide RRAMD. Veksler, Gennadi Bersuker, A. W. Bushmaker, P. R. Shrestha, K. P. Cheung, Jason P. Campbell. 1-5 [doi]
- SiC Power MOSFETs: Designing for Reliability in Wide-Bandgap SemiconductorsKevin Matocha, In-Hwan Ji, Xuning Zhang, Sauvik Chowdhury. 1-8 [doi]
- Evaluating Impact of Information Uncertainties on Component Reliability AssessmentDiganta Das, Edmond Elburn, Michael G. Pecht, Bhanu Sood. 1-9 [doi]
- Reliability of CMOS Integrated Memristive HfO2 Arrays with Respect to Neuromorphic ComputingM. K. Mahadevaiah, E. Perez, Christian Wenger, Alessandro Grossi, Cristian Zambelli, Piero Olivo, F. Zahari, H. Kohlstedt, M. Ziegler. 1-4 [doi]
- Reliability Limiting Defects in MOS Gate Oxides: Mechanisms and Modeling ImplicationsDaniel M. Fleetwood. 1-10 [doi]
- Do Solar Proton Events Reduce the Number of Faults in Supercomputers?: A Comparative Analysis of Faults During and without Solar Proton EventsClaire McKay Bowen, Nathan DeBardeleben, Sean Blanchard, Christine M. Anderson-Cook. 1-5 [doi]
- Negative and Positive Muon-Induced SEU Cross Sections in 28-nm and 65-nm Planar Bulk CMOS SRAMsWang Liao, Masanori Hashimoto, Seiya Manabe, Yukinobu Watanabe, Shin-ichiro Abe, Keita Nakano, Hayato Takeshita, Motonobu Tampo, Soshi Takeshita, Yasuhiro Miyake. 1-5 [doi]
- A Novel HV-NPN ESD Protection Device with Buried Floating P-Type ImplantJie Jack Zeng, Ruchil Jain, Kyong Jin Hwang, Robert Gauthier. 1-4 [doi]
- Long Term NBTI Relaxation Under AC and DC Biased Stress and RecoveryElnatan Mataev, James H. Stathis, Giuseppe La Rosa, Barry P. Linder. 1-5 [doi]
- Aging-Aware Design Verification Methods Under Real Product Operating ConditionsHyewon Shim, Jeongmin Jo, Yoohwan Kim, Bongyong Jeong, Minji Shon, Hai Jiang, Sangwoo Pae. 1-4 [doi]
- Automatic Data Repair Overwrite Pulse for 3D-TLC NAND Flash Memories with 38x Data-Retention Lifetime ExtensionKyoji Mizoguchi, Kyosuke Maeda, Ken Takeuchi. 1-5 [doi]
- Avalanche and Short-Circuit Robustness of 4600 V SiC DMOSFETsSiddarth Sundaresan, Vamsi Mulpuri, Stoyan Jeliazkov, Ranbir Singh. 1-7 [doi]
- Influence of Donor-Type Hole Traps Under P-GaN Gate in GaN-Based Gate Injection Transistor (GIT)Kenichiro Tanaka, Masahiro Hikita, Tetsuzo Ueda. 1-4 [doi]
- Impact of Passive & Active Load Gate Impedance on Breakdown Hardness in 28nm FDSOI TechnologyA. P. Nguyen, X. Garros, M. Rafik, F. Cacho, D. Roy, X. Federspiel, F. Gaillard. 1-5 [doi]
- Reliability Perspective on Neuromorphic Computing Based on Analog RRAMHuaqiang Wu, Meiran Zhao, Yuyi Liu, Peng Yao, Yue Xi, Xinyi Li, Wei Wu, Qingtian Zhang, Jianshi Tang, Bin Gao 0006, He Qian. 1-4 [doi]
- Machine Learning for Detection of Competing Wearout MechanismsShu-Han Hsu, Kexin Yang, Linda Milor. 1-9 [doi]
- Hot-Electron Effects in GaN GITs and HD-GITs: A Comprehensive AnalysisEric E. Fabris, Matteo Meneghini, Carlo De Santi, Matteo Borga, Gaudenzio Meneghesso, Enrico Zanoni, Y. Kinoshita, K. Tanaka, H. Ishida, T. Ueda. 1-6 [doi]
- A New Time Efficient Methodology for the Massive Characterization of RTN in CMOS DevicesG. Pedreira, Javier Martín-Martínez, Javier Diaz-Fortuny, P. Saraza-Canflanca, Rosana Rodríguez, R. Castro-López, Elisenda Roca, Francisco V. Fernández, Montserrat Nafría. 1-5 [doi]
- On the Frequency Dependence of Bulk Trap Generation During AC Stress in Si and SiGe RMG P-FinFETsNarendra Parihar, Uma Sharma, Richard G. Southwick, Miaomiao Wang, James H. Stathis, Souvik Mahapatra. 1-8 [doi]
- Soft Error Performance of High-Speed Pulsed-DICE-Latch Design in 16 nm and 7 nm FinFET ProcessesBalaji Narasimham, K. Chandrasekharan, J. K. Wang, Bharat L. Bhuva. 1-4 [doi]
- Physical Insights into the Low Current ESD Failure of LDMOS-SCR and its Implication on Power ScalabilityNagothu Karmel Kranthi, B. Sampath Kumar, Akram A. Salman, Gianluca Boselli, Mayank Shrivastava. 1-5 [doi]
- Robust BEOL MIMCAP for Long and Controllable TDDB LifetimeLili Cheng, Seungman Choi, Sean P. Ogden, Teck Jung Tang, Robert Fox. 1-3 [doi]
- Investigation of NBTI Dynamic Behavior with Ultra-Fast MeasurementFlorian Cacho, X. Federspiel, D. Nouguier, C. Diouf. 1-6 [doi]
- Bilayer Passivation Film for Cu Interconnects on Si Interconnect FabricNiloofar Shakoorzadeh, Amir Hanna, Subramanian Iyer. 1-5 [doi]
- Reliability Evaluation of Silicon Interconnect Fabric TechnologyKannan K. Thankappan, Adeel Ahmad Bajwa, Boris Vaisband, SivaChandra Jangam, Subramanian S. Iyer. 1-5 [doi]
- Permanent and Transient Effects of High-Temperature Bias Stress on Room- Temperature $V_{T}$ Drift Measurements in SiC Power MOSFETsDaniel B. Habersat, Ronald Green, Aivars J. Lelis. 1-4 [doi]
- Bias Temperature Instability Reliability in Stacked Gate-All-Around Nanosheet TransistorMiaomiao Wang, Jingyun Zhang, Huimei Zhou, Richard G. Southwick, Robin Hsin Kuo Chao, Xin Miao, Veeraraghavan S. Basker, Tenko Yamashita, Dechao Guo, Gauri Karve, Huiming Bu, James H. Stathis. 1-6 [doi]
- Fundamental Understanding of Oxide Defects in HfO2 and Y2O3 on GaAs(001) with High Thermal StabilityH. W. Wan, Y. J. Hong, L. B. Young, M. Hong, J. Kwo. 1-4 [doi]
- Process Optimization for HCI Improvement in I/O Analog DevicesC. Diouf, N. Guitard, M. Rafik, J. J. Martinez, X. Federspiel, Alain Bravaix, D. Muller, D. Roy. 1-6 [doi]
- Accelerated Capture and Emission (ACE) Measurement Pattern for Efficient BTI Characterization and ModelingZhicheng Wu, Jacopo Franco, Dieter Claes, Gerhard Rzepa, Philippe J. Roussel, Nadine Collaert, Guido Groeseneken, Dimitri Linten, Tibor Grasser, Ben Kaczer. 1-7 [doi]
- GIDL Increase Due to HCI Stress: Correlation Study of MOSFET Degradation Parameters and Modelling for Reliability SimulationEdoardo Ceccarelli, Kevin Manning, Seamus Maxwell, Colm Heffernan. 1-5 [doi]
- Low Voltage Transient RESET Kinetic Modeling of OxRRAM for Neuromorphic ApplicationsJonas Doevenspeck, Robin Degraeve, Andrea Fantini, Peter Debacker, Diederik Verkest, Rudy Lauwereins, Wim Dehaene. 1-6 [doi]
- Modelling Degradation of Matched-Circuits in Operational Conditions: Active and Stand-by ModesKhai Nguyen, Geoff Liang. 1-5 [doi]
- Distinguishing Interfacial Hole Traps in (110), (100) High-K Gate StackYueyang Liu, Xiangwei Jiang, Liwei Wang 0003, Yunfei En, Runsheng Wang. 1-4 [doi]
- Efficient Simulation of Electromigration Damage in Large Chip Power Grids Using Accurate Physical Models (Invited Paper)Farid N. Najm, Valeriy Sukharev. 1-10 [doi]
- Design and Optimization of the NAND ESD Clamp in CMOS TechnologyJian Liu, Nathaniel Peachey. 1-4 [doi]
- Program/Erase Cycling Enhanced Lateral Charge Diffusion in Triple-Level Cell Charge-Trapping 3D NAND Flash MemoryRui Cao, Jixuan Wu, Wenjing Yang, Jiezhi Chen, Xiangwei Jiang. 1-4 [doi]
- Stability in Fluorine-Treated Al-Rich High Electron Mobility Transistors with 85% Al-Barrier CompositionAlbert G. Baca, B. A. Klein, A. M. Armstrong, A. A. Allerman, E. A. Douglas, T. R. Fortune, R. J. Kaplar. 1-4 [doi]
- Comparative Analysis of the Degradation Mechanisms in Logic and I/O FinFET Devices Induced by Plasma DamageGaspard Hiblot, Yefan Liu, Geert Hellings, Geert Van der Plas. 1-5 [doi]
- Influence of Gate Length on pBTI in GaN-on-Si E-Mode MOSc-HEMTA. G. Viey, W. Vandendaele, M.-A. Jaud, R. Gwoziecki, A. Torres, M. Plissonnier, F. Gaillard, G. Ghibaudo, R. Modica, F. Iucolano, Matteo Meneghini, Gaudenzio Meneghesso. 1-6 [doi]
- Current Filament Dynamics Under ESD Stress in High Voltage (Bidirectional) SCRs and It's Implications on Power Law BehaviorNagothu Karmel Kranthi, Akram A. Salman, Gianluca Boselli, Mayank Shrivastava. 1-5 [doi]
- Low-Frequency Noise Reduction in 22FDX®: Impact of Device Geometry and Back BiasLuca Pirro, A. Zaka, O. Zimmerhackl, T. Hermann, M. Otto, E. M. Bazizi, Jan Hoentschel, X. Li, R. Taylor. 1-5 [doi]
- Stability of 4H-SiC JBS Diodes Under Repetitive Avalanche StressAjit Kanale, Kijeong Han, B. Jayant Baliga, Subhashish Bhattacharya. 1-6 [doi]
- From Emerging Memory to Novel Devices for Neuromorphic Systems: Consequences for the Reliability Requirements of Memristive DevicesD. J. Wouters. 1-4 [doi]
- SEIFF: Soft Error Immune Flip-Flop for Mitigating Single Event Upset and Single Event Transient in 10 nm FinFETTaiki Uemura, Soonyoung Lee, Dahye Min, Ihlhwa Moon, Seungbae Lee, Sangwoo Pae. 1-6 [doi]
- High Voltage Tolerant Design with Advanced Process for TV ApplicationS. E. Liu, M.-H. Hsieh, Y. R. Chen, J. Y. Jao, M. Z. Lin, Y. H. Fang, M. J. Lin. 1-4 [doi]
- A Statistical Learning Model for Accurate Prediction of Time-Dependent Dielectric Degradation for Low Failure RatesKaustubh Joshi, Yung-Huei Lee, Yu-Cheng Yao, Shu-Wen Chang, Siao-Syong Bian, P. J. Liao, Jiaw-Ren Shih, Min-Jan Chen. 1-6 [doi]
- Reliability Analysis of a Delay-Locked Loop Under HCI and BTI DegradationTonmoy Dhar, Sachin S. Sapatnekar. 1-6 [doi]
- Characterization and Analysis of Bit Errors in 3D TLC NAND Flash MemoryNikolaos Papandreou, Haralampos Pozidis, Thomas P. Parnell, Nikolas Ioannou, Roman A. Pletka, Sasa Tomic, Patrick Breen, Gary A. Tressler, Aaron Fry, Timothy Fisher. 1-6 [doi]
- Gaining Confidence - A Review of Silicon Carbide's Reliability StatusNando Kaminski, Sarah Rugen, Felix Hoffmann. 1-7 [doi]
- D} bias spaceErik Bury, Adrian Chasin, Michiel Vandemaele, Simon Van Beek, Jacopo Franco, Ben Kaczer, Dimitri Linten. 1-6 [doi]
- Reinforcement Learning System Comprising Resistive Analog Neuromorphic DevicesSong-Ju Kim, Kaori Ohkoda, Masashi Aono, Hisashi Shima, Makoto Takahashi, Yasuhisa Naitoh, Hiroyuki Akinaga. 1-6 [doi]
- Design-For-Reliability Flow in 7nm Products with Data Center and Automotive ApplicationsJae-Gyung Ahn, I-Ru Chen, Ping-Chin Yeh, Jonathan Chang. 1-5 [doi]
- Wafer Level Approach for the Investigation of the Long-Term Stability of Resistive Platinum Devices at Elevated TemperaturesTimo Schossler, Florian Schon, Christian Lemier, Gerald Urban. 1-5 [doi]
- Applying Machine Learning to Design for Reliability CoverageNorman Chang, Wentze Chuang, Ganesh Kumar Tsavatanalli, Joao Geada, Hao Zhuang, Sankar Ramachandran, Rahul Rajan, Ying Shiun Li, Yaowei Jia, Mathew Kaipanatu, Suresh Kumar Mantena, Ming-Chih Shih, Anita Yang, Roger Jang. 1-7 [doi]
- Product Reliability Methods to Enable High Performance CPU'sRoman Rechter, Robert Kwasnick, Almog Reshef, Oren Zonensain, Tal Raz, Anisur Rahman, Praveen Polasam, Maxim Levit. 1-5 [doi]
- A Physical-Statistical Approach to AlGaN/GaN HEMT ReliabilityPeter Moens, Arno Stockman. 1-6 [doi]
- Single-Event Upset Responses of Dual- and Triple-Well D Flip-Flop Designs in 7-nm Bulk FinFET TechnologyL. Xu, J. Cao, B. L. Bhuva, Indranil Chatterjee, S.-J. Wen, R. Wong, Lloyd W. Massengill. 1-5 [doi]
- Superior Endurance Performance of 22-nm Embedded MRAM TechnologyV. B. Naik, J.-H. Lim, K. Yamane, D. Zeng, H. Yang, N. Thiyagarajah, J. H. Kwon, N. L. Chung, R. Chao, T. Ling, K. Lee. 1-4 [doi]
- Study of the Mechanical Stress Impact on Silicide Contact Resistance by 4-Point BendingYefan Liu, Hao Yu, Gaspard Hiblot, Anastasiia Kruv, Marc Schaekers, Naoto Horiguchi, Dimitrios Velenis, Ingrid De Wolf. 1-5 [doi]
- Concise Analytical Expression for Wunsch-Bell 1-D Pulsed Heating and Applications in ESD Using TLPGeert Hellings, Philippe Roussel, Nian Wang, Roman Boschke, Shih-Hung Chen, Marko Simicic, Mirko Scholz, Soeren Stoedel, Kris Myny, Dimitri Linten, Paul Hellings, Nowab Reza M. D. Ashif. 1-6 [doi]
- Variation-Aware Physics-Based Electromigration Modeling and Experimental Calibration for VLSI InterconnectsSarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori, Houman Zahedmanesh, Kristof Croes, Kevin Garello, Gouri Sankar Kar, Francky Catthoor. 1-6 [doi]
- Response of Switching Hole Traps in the Small-Area P-MOSFET Under Channel Hot-Hole EffectX. Ju, D. S. Ang. 1-4 [doi]
- Characterization and Modelling of High Speed Ge Photodetectors ReliabilityF. Sy, Q. Rafhay, Julien Poette, G. Grosa, C. Besset, G. Beylier, P. Grosse, D. Roy, Jean-Emmanuel Broquin. 1-5 [doi]
- Recent Updates to Transistor Level Reliability AnalysisArt Schaldenbrand, Jushan Xie, Hany Elhak. 1-8 [doi]
- Enhanced Fail Rate Projections Using Negative Design Assist in Automotive Grade SRAMsSriram Balasubramanian, Hari Balan, Lei Liu, Kevin Khua, Wah-Peng Neo, Dianji Sui, Tze Ho Simon Chan. 1-4 [doi]
- An Evaluation of X-Ray Irradiation Induced Dynamic Refresh Characterization in DRAMKyungwoo Lee, Chae-Hyuk Yun, HyungAh Seo, Taehun Kang, Yunsung Lee, Kangyong Cho. 1-3 [doi]
- A Comprehensive Wafer Level Reliability Study on 65nm Silicon InterposerC. S. Premachandran, Thuy Tran-Quinn, Lloyd Burrell, Patrick Justison. 1-8 [doi]
- Localized Layout Effect Related Reliability Approach in 8nm FinFETs Technology: From Transistor to CircuitHai Jiang, Hyun-Chul Sagong, Jinju Kim, Junekyun Park, Sangchul Shin, Sangwoo Pae. 1-5 [doi]
- Performance Improvement on HfO2-Based 1T Ferroelectric NVM by Electrical PreconditioningCarlo Cagli, Luca Perniola, F. Gaillard, S. Duenkel, T. Melde, B. Mueller, M. Trentzsch, S. Wittek, S. Beyer. 1-4 [doi]
- Assesment of CPI Stress Impact on IC Reliability and Performance in 2.5D/3D PackagesArmen Kteyan, Henrik Hovsepyan, Jun-Ho Choy, Valeriy Sukharev. 1-7 [doi]
- Impact of Combinational Logic Delay for Single Event Upset on Flip Flops in a 65 nm FDSOI ProcessJun Furuta, Yuto Tsukita, Kodai Yamada, Mitsunori Ebara, Kentaro Kojima, Kazutoshi Kobayashi. 1-4 [doi]
- Advanced Circuit Reliability Verification for Robust DesignAntony Fan, Joddy Wang, Vladimir Aptekar. 1-8 [doi]
- Hot Carrier Reliability Improvement of Thicker Gate Oxide nFET Devices in Advanced FinFETsM. Iqbal Mahmud, A. Gupta, Maria Toledano-Luque, N. Mavilla, J. Johnson, P. Srinivasan, A. Zainuddin, S. Rao, S. Cimino, B. Min, Tanya Nigam. 1-6 [doi]
- Investigation on Latch-Up Path Between I/O PMOS and Core PMOS in a 0.18-μm CMOS ProcessChun-Cheng Chen, Ming-Dou Ker. 1-4 [doi]
- d) Bias Space Modeling of Hot-Carrier Degradation in Nanowire FETsMichiel Vandemaele, Ben Kaczer, Stanislav Tyaginov, Zlatan Stanojevic, Alexander Makarov, Adrian Chasin, Erik Bury, Hans Mertens, Dimitri Linten, Guido Groeseneken. 1-7 [doi]
- Reliability and Performance Issues in SiC MOSFETs: Insight Provided by Spin Dependent RecombinationJames P. Ashton, Patrick M. Lenahan, Daniel J. Lichtenwalner, Aivars J. Lelis, Mark A. Anders. 1-5 [doi]
- Role of Defects in the Reliability of HfO2/Si-Based Spacer Dielectric Stacks for Local InterconnectsChen Wu, Adrian Chasin, A. Padovani, Alicja Lesniewska, Steven Demuynck, Kris Croes. 1-6 [doi]
- Investigating the Aging Dynamics of Diode-Connected MOS Devices Using an Array-Based Characterization Vehicle in a 65nm ProcessNakul Pande, Gyusung Park, Chris H. Kim, Srikanth Krishnan, Vijay Reddy. 1-6 [doi]
- Degradation Monitoring - from a Vision to RealityEvelyn Landman, Shai Cohen, Noam Brousard, Raanan Gewirtzman, Inbar Weintrob, Eyal Fayne, Yahel David, Yuval Bonen, Omer Niv, Shai Tzroia, Alex Burlak, J. W. McPherson. 1-4 [doi]
- Perimeter Driven Transport in the p-GaN Gate as a Limiting Factor for Gate ReliabilitySteve Stoffels, Niels Posthuma, Stefaan Decoutere, Benoit Bakeroot, A. N. Tallarico, Enrico Sangiorgi, Claudio Fiegna, J. Zheng, X. Ma, Matteo Borga, Elena Fabris, Matteo Meneghini, Enrico Zanoni, Gaudenzio Meneghesso, Juraj Priesol, Alexander Satka. 1-10 [doi]
- New Access to Soft Breakdown Parameters of Low-k Dielectrics Through Localisation-Based AnalysisNorbert Herfurth, Anne Beyreuther, Elham Amini, Christian Boit, Michél Simon-Najasek, Susanne Hübner, Frank Altmann, R. Herfurth, C. Wu, I. De Wolf, K. Croes. 1-9 [doi]
- A Simple Prediction Method for Chip-Level Electromigration Lifetime Using Generalized Gamma DistributionShinji Yokogawa, Kyosuke Kunii. 1-6 [doi]
- Design Strategies for Rugged SiC Power DevicesDiana Xing, Tianshi Liu, Susanna Yu, Minseok Kang, Arash Salemi, Marvin White, Anant Agarwal. 1-5 [doi]
- Plasma Antenna Charging in CMOS Image SensorsY. Sacchettini, J.-P. Carrere, Vincent Goiffon, Pierre Magnan. 1-5 [doi]
- Probing Write Error Rate and Random Telegraph Noise of MgO Based Magnetic Tunnel Juction Using a High Throughput Characterization SystemShifan Gao, Bing Chen, Nuo Xu, Yiming Qu, Yi Zhao. 1-4 [doi]
- A New Approach to Validate GaN FET Reliability to Power-Line Surges Under Use-ConditionsSandeep R. Bahl, Paul Brohlin. 1-4 [doi]
- Physics to Tapeout: The Challenge of Scaling Reliability VerificationSridhar Srinivasan, Matthew Hogan. 1-5 [doi]
- CPI Reliability Challenges of Large Flip Chip Packages and Effects of Kerf Size and SubstrateZhuo-Jie Wu, Manish Nayini, Charles Carey, Samantha Donovan, David Questad, Edmund D. Blackshear. 1-7 [doi]
- Wafer-Scale TaOx Device Variability and Implications for Neuromorphic Computing ApplicationsChristopher H. Bennett, Diana Garland, Robin B. Jacobs-Gedrim, Sapan Agarwal, Matthew J. Marinella. 1-4 [doi]
- Thin-Film FD-SOI BIMOS Topologies for ESD ProtectionLouise De Conti, Sorin Cristoloveanu, Maud Vinet, Philippe Galy. 1-5 [doi]
- Nonlinear Mixed Model and Reliability Prediction for OLED Luminance DegradationKanghyun Choi, Jongwon Lee, Jongwoo Park. 1-4 [doi]
- Stress Migration Followed by Electromigration Reliability TestingJ. M. Passage, N. Azhari, J. R. Lloyd. 1-5 [doi]
- Current Crowding Impact on Electromigration in Al InterconnectsYoung Joon Park, Jungwoo Joh, Jayhoon Chung, Srikanth Krishnan. 1-6 [doi]
- Low-Frequency Noise Measurements to Characterize Cu-Electromigration Down to 44nm Metal PitchSofie Beyne, Olalla Varela Pedreira, Ingrid De Wolf, Zsolt Tokei, Kristof Croes. 1-6 [doi]
- Gate-Stack Engineered NBTI Improvements in Highvoltage Logic-For-Memory High-ĸ/Metal Gate DevicesBarry J. O'Sullivan, Romain Ritzenthaler, Gerhard Rzepa, Z. Wu, E. Dentoni Litta, O. Richard, T. Conard, V. Machkaoutsan, Pierre Fazan, C. Kim, Jacopo Franco, Ben Kaczer, Tibor Grasser, Alessio Spessot, Dimitri Linten, N. Horiguchi. 1-8 [doi]
- Reliability of 8Mbit Embedded-STT-MRAM in 28nm FDSOI TechnologyY. Ji, H. J. Goo, J. Lim, S. B. Lee, S. Lee, T. Uemura, J. C. Park, S. I. Han, S. C. Shin, J. H. Lee, Y. J. Song, K. M. Lee, H. M. Shin, S.-H. Hwang, B. Y. Seo, Y. K. Lee, J. C. Kim, G. H. Koh, K. C. Park, S. Pae, G. T. Jeong, J.-S. Yoon, E. S. Jung. 1-3 [doi]
- Comparative Study of TDDB Models on BEOL Interconnects for Sub-20 nm SpacingsNiaz Mahmud, Nabihah Azhari, J. R. Lloyd. 1-4 [doi]
- First Demonstration and Physical Insights into Time-Dependent Breakdown of Graphene Channel and InterconnectsAbhishek Mishra, Adil Meersha, Nagothu Karmel Kranthi, Kruti Trivedi, Harsha B. Variar, N. S. Veenadhari Bellamkonda, Srinivasan Raghavan, Mayank Shrivastava. 1-6 [doi]
- Use of High Voltage OBIRCH Fault Isolation Technique in Failure Analysis of High Voltage IC'sChenran Lei, Albert Lee, Qinkan Kang, Minkwang Lee, Seiji Yang, Dan Oliver, Tu Giao. 1-4 [doi]
- eNVM MRAM Retention Reliability Modeling in 22FFL FinFET TechnologyJames A. O'Donnell, Chris Connor, Tanmoy Pramanik, Jeff Hicks, Juan G. Alzate, Fatih Hamzaoglu, Justin Brockman, Oleg Golonzka, Kevin Fischer. 1-3 [doi]
- Utilizing a Thorough Understanding of Critical Aging and Failure Mechanisms in finFET Technologies to Enable Reliable High Performance CircuitsBonnie E. Weir, Vani Prasad, Shahriar Moinian, SangJune Park, Joseph Blasko, Jason Brown, Jayanthi Pallinti. 1-5 [doi]
- Correct Extrapolation Model for TDDB of STT-MRAM MgO Magnetic Tunnel JunctionsJ.-H. Lim, N. Raghavan, V. B. Naik, J. H. Kwon, K. Yamane, H. Yang, K. H. Lee, K. L. Pey. 1-7 [doi]
- Time Dependent Dielectric Breakdown of Cobalt and Ruthenium Interconnects at 36nm PitchH. Huang, P. S. McLaughin, J. J. Kelly, C.-C. Yang, R. G. Southwick, M. Wang, G. Bonilla, G. Karve. 1-5 [doi]
- Gate Stability and Robustness of In-Situ Oxide GaN Interlayer Based Vertical Trench MOSFETs (OG-FETs)Maria Ruzzarin, Matteo Borga, Enrico Zanoni, Matteo Meneghini, Gaudenzio Meneghesso, Dong Ji, Wenwen Li, Silvia H. Chan, Anchal Agarwal, Chirag Gupta, Stacia Keller, Umesh K. Mishra, Srabanti Chowdhury. 1-5 [doi]
- Comprehensive Analysis of Data-Retention and Endurance Trade-Off of 40nm TaOx-based ReRAMShouhei Fukuyama, Atsuna Hayakawa, Ryutaro Yasuhara, Shinpei Matsuda, Hiroshi Kinoshita, Ken Takeuchi. 1-6 [doi]
- Tunable Holding-Voltage High Voltage ESD DevicesJian-Hsing Lee, Natarajan Mahadeva Iyer. 1-8 [doi]
- BTI Characterization of MBE Si-Capped Ge Gate Stack and Defect Reduction via Forming Gas AnnealingH. W. Wan, Y. J. Hong, Y. T. Cheng, M. Hong. 1-4 [doi]
- On the Effect of NBTI Induced Aging of Power Stage on the Transient Performance of On-Chip Voltage RegulatorsVenkata Chaitanya Krishna Chekuri, Arvind Singh, Nihar Dasari, Saibal Mukhopadhyay. 1-5 [doi]
- VTH-Hysteresis and Interface States Characterisation in SiC Power MOSFETs with Planar and Trench GateBesar Asllani, Alberto Castellazzi, Oriol Avino-Salvado, Asad Fayyaz, Hervé Morel, Dominique Planson. 1-6 [doi]
- Experimental Study on Effects of Boron Transient Enhanced Diffusion on Channel Size Dependences of Low Frequency Noise in NMOSFETsShuntaro Fujii, Isao Maru, Soichi Morita, Tsutomu Miyazaki. 1-5 [doi]