Sarath Mohanachandran Nair - researchr alias

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Viewing Publication 1 - 18 from 18

2020

Special Session - Emerging Memristor Based Memory and CIM Architecture: Test, Repair and Yield AnalysisRajendra Bishnoi, Lizhou Wu, Moritz Fieback, Christopher Münch, Sarath Mohanachandran Nair, Mehdi Baradaran Tahoori, Ying Wang, Huawei Li, Said Hamdioui. vts 2020: 1-10 [doi]

Variation Analysis, Fault Modeling and Yield Improvement of Emerging Spintronic MemoriesSarath Mohanachandran Nair. PhD thesis, Karlsruhe University, Germany, 2020. [doi]

Defect Characterization and Test Generation for Spintronic-based Compute-In-MemorySarath Mohanachandran Nair, Christopher Münch, Mehdi Baradaran Tahoori. ets 2020: 1-6 [doi]

Mitigating Read Failures in STT-MRAMSarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori. vts 2020: 1-6 [doi]

Dynamic Faults based Hardware Trojan Design in STT-MRAMSarath Mohanachandran Nair, Rajendra Bishnoi, Arunkumar Vijayan, Mehdi Baradaran Tahoori. date 2020: 933-938 [doi]

Physics based modeling of bimodal electromigration failure distributions and variation analysis for VLSI interconnectsSarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi B. Tahoori, Houman Zahedmanesh, Kristof Croes, Kevin Garello, Gouri Sankar Kar, Francky Catthoor. irps 2020: 1-5 [doi]

A Universal Spintronic Technology based on Multifunctional Standardized StackMehdi Baradaran Tahoori, Sarath Mohanachandran Nair, Rajendra Bishnoi, L. Torres, Sophiane Senni, Guillaume Patrigeon, P. Benoit, Gregory di Pendina, Guillaume Prenat. date 2020: 394-399 [doi]

2019

A Spintronics Memory PUF for Resilience Against Cloning CounterfeitSamir Ben Dodo, Rajendra Bishnoi, Sarath Mohanachandran Nair, Mehdi Baradaran Tahoori. tvlsi, 27(11):2511-2522, 2019. [doi]

A Comprehensive Framework for Parametric Failure Modeling and Yield Analysis of STT-MRAMSarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori. tvlsi, 27(7):1697-1710, 2019. [doi]

Variation-Aware Physics-Based Electromigration Modeling and Experimental Calibration for VLSI InterconnectsSarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori, Houman Zahedmanesh, Kristof Croes, Kevin Garello, Gouri Sankar Kar, Francky Catthoor. irps 2019: 1-6 [doi]

Variation-aware Fault Modeling and Test Generation for STT-MRAMSarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori, H. Grigoryan, G. Tshagharyan. iolts 2019: 80-83 [doi]

2018

VAET-STT: Variation Aware STT-MRAM Analysis and Design Space Exploration ToolSarath Mohanachandran Nair, Rajendra Bishnoi, Mohammad Saber Golanbari, Fabian Oboril, Fazal Hameed, Mehdi Baradaran Tahoori. tcad, 37(7):1396-1407, 2018. [doi]

Parametric failure modeling and yield analysis for STT-MRAMSarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori. date 2018: 265-268 [doi]

Defect injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAMSarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori, G. Tshagharyan, H. Grigoryan, Gurgen Harutyunyan, Yervant Zorian. itc 2018: 1-10 [doi]

Process variation and temperature aware adaptive scrubbing for retention failures in STT-MRAMNour Sayed, Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori. aspdac 2018: 203-208 [doi]

2017

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