Abstract is missing.
- Voltage Noise Analysis with Ring Oscillator ClocksLucas Machado, Antoni Roca Perez, Jordi Cortadella. 1-6 [doi]
- Resilient Cell-Based Architecture for Time-to-Digital ConverterChia-Hua Wu, Shi-Yu Huang, Mason Chern, Yung-Fa Chou, Ding-Ming Kwai. 7-12 [doi]
- Reconfigurable Support Vector Machine Classifier with Approximate ComputingMartin Van Leussen, Jos Huisken, Lei Wang, Hailong Jiao, José Pineda de Gyvez. 13-18 [doi]
- Unconventional Layout Techniques for a High Performance, Low Variability Subthreshold Standard Cell LibraryJordan Morris, Pranay Prabhat, James Myers, Alex Yakovlev. 19-24 [doi]
- SiLago-CoG: Coarse-Grained Grid-Based Design for Near Tape-Out Power Estimation Accuracy at High LevelSyed Mohammad Asad Hassan Jafri, Nasim Farahini, Ahmed Hemani. 25-31 [doi]
- High Speed Power Efficient Carry Select Adder DesignRaghava Katreepalli, Themistoklis Haniotakis. 32-37 [doi]
- Architecting SOT-RAM Based GPU Register FileSparsh Mittal, Rajendra Bishnoi, Fabian Oboril, Haonan Wang, Mehdi Baradaran Tahoori, Adwait Jog, Jeffrey S. Vetter. 38-44 [doi]
- RIMPA: A New Reconfigurable Dual-Mode In-Memory Processing Architecture with Spin Hall Effect-Driven Domain Wall Motion DeviceShaahin Angizi, Zhezhi He, Farhana Parveen, Deliang Fan. 45-50 [doi]
- Area and Delay Efficient Design of a Quantum Bit String ComparatorHafiz Md. Hasan Babu, Lafifa Jamal, Sayanton Vhaduri Dibbo, Ashis Kumer Biswas. 51-56 [doi]
- Novel Pulsed-Latch Replacement in Non-Volatile Flip-Flop CoreHao Cai, You Wang, Lirida A. B. Naviner, Weisheng Zhao. 57-61 [doi]
- Analysis of RRAM Reliability Soft-Errors on the Performance of RRAM-Based Neuromorphic SystemsAmr M. S. Tosson, Shimeng Yu, Mohab H. Anis, Lan Wei. 62-67 [doi]
- Design of Quantum Circuits for Galois Field Squaring and ExponentiationEdgard Muñoz-Coreas, Himanshu Thapliyal. 68-73 [doi]
- STBC: Side Channel Attack Tolerant Balanced Circuit with Reduced Propagation DelayHyunmin Kim, Seokhie Hong, Bart Preneel, Ingrid Verbauwhede. 74-79 [doi]
- AICNN: Implementing Typical CNN Algorithms with Analog-to-Information Conversion ArchitectureKaige Jia, Zheyu Liu, Fei Qiao, Xinjun Liu, Qi Wei, Huazhong Yang. 80-85 [doi]
- Efficient FPGA Implementation of the SHA-3 Hash FunctionMagnus Sundal, Ricardo Chaves. 86-91 [doi]
- Decoupling Translation Lookaside Buffer Coherence from Cache CoherenceHao Liu, Quentin L. Meunier, Alain Greiner. 92-97 [doi]
- Centrality Indicators for Efficient and Scalable Logic MaskingBrice Colombier, Lilian Bossuet, David Hély. 98-103 [doi]
- Combined TDM and SDM Circuit Switching NoCs with Dedicated Connection AllocatorYong Chen, Emil Matús, Gerhard P. Fettweis. 104-109 [doi]
- Efficient Single-Precision Floating-Point Division Using Harmonized Parabolic SynthesisSüleyman Savas, Erik Hertz, Tomas Nordström, Zain-ul-Abdin. 110-115 [doi]
- An Efficient Design of an FPGA-Based Multiplier Using LUT Merging TheoremZarrin Tasnim Sworna, Mubin Ul Haque, Hafiz Md. Hasan Babu, Lafifa Jamal, Ashis Kumer Biswas. 116-121 [doi]
- High-Performance and Energy-Efficient 256-Bit CMOS Priority EncoderDimitrios Balobas, Nikos Konofaos. 122-127 [doi]
- Improving FPGA Design with Monolithic 3D Integration Using High Dense Inter-Stack ViaSrivatsa Rangachar Srinivasa, Karthik Mohan, Wei-Hao Chen, Kuo-Hsinag Hsu, Xueqing Li, Meng-Fan Chang, Sumeet Kumar Gupta, John Sampson, Vijaykrishnan Narayanan. 128-133 [doi]
- Floating-Point Arithmetic Using GPGPU on FPGAsMuhammed Al Kadi, Benedikt Janßen, Michael Hübner. 134-139 [doi]
- Minimizing Critical Access Time for 3D Data Bus Based on Inserted Bus Switches and RepeatersChia-Chun Tsai. 140-145 [doi]
- Sample Preparation on Micro-Electrode-Dot-Array Digital Microfluidic BiochipsZipeng Li, Kelvin Yi-Tse Lai, Krishnendu Chakrabarty, Tsung-Yi Ho, Chen-Yi Lee. 146-151 [doi]
- Hybrid Polymorphic Logic Gate with 5-Terminal Magnetic Domain Wall Motion DeviceFarhana Parveen, Zhezhi He, Shaahin Angizi, Deliang Fan. 152-157 [doi]
- Ultra-Low Energy Data Driven Computing Using Asynchronous Micropipelines and Nano-Electro-Mechanical RelaysHaider Alrudainy, Andrey Mokhov, Fei Xia, Alex Yakovlev. 158-163 [doi]
- Inverter Propagation and Fan-Out Constraints for Beyond-CMOS Majority-Based TechnologiesEleonora Testa, Odysseas Zografos, Mathias Soeken, Adrien Vaysset, Mauricio Manfrini, Rudy Lauwereins, Giovanni De Micheli. 164-169 [doi]
- BioViz: An Interactive Visualization Engine for the Design of Digital Microfluidic BiochipsJannis Stoppe, Oliver Keszocze, Maximilian Luenert, Robert Wille, Rolf Drechsler. 170-175 [doi]
- Scouting Logic: A Novel Memristor-Based Logic Design for Resistive ComputingLei Xie, H. A. Du Nguyen, Jintao Yu, Ali Kaichouhi, Mottaqiallah Taouil, Mohammad AlFailakawi, Said Hamdioui. 176-181 [doi]
- Latency Aware Block Replacement for L1 Caches in Chip MultiprocessorShirshendu Das, Hemangee K. Kapoor. 182-187 [doi]
- Wireless NoCs Using Directional and Substrate Propagation AntennasVasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin, Kapil R. Dandekar. 188-193 [doi]
- A Multi-Gbps Fully Pipelined Layered Decoder for IEEE 802.11n/ac/ax LDPC CodesSaleh Usman, Mohammad M. Mansour, Ali Chehab. 194-199 [doi]
- A Meta-Routing Method to Create Multiple Virtual Logical Networks on a Single Hardware NoCHela Belhadj Amor, Hamed Sheibanyrad, Frédéric Pétrot. 200-205 [doi]
- Secured-by-Design FPGA against Early EvaluationZiyad Almohaimeed, Mihai Sima. 206-212 [doi]
- Customizing Skewed Trees for Fast Memory Integrity Verification in Embedded SystemsSaru Vig, Tan Yng Tzer, Guiyuan Jiang, Siew Kei Lam. 213-218 [doi]
- A New High Performance VLSI Architecture for LMS Adaptive Filter Using Distributed ArithmeticMohd Tasleem Khan, Shaik Rafi Ahamed. 219-224 [doi]
- Ultra High Throughput Unrolled Layered Architecture for QC-LDPC DecodersOana Boncalo, Alexandru Amaricai. 225-230 [doi]
- A General Design Framework for Sparse Parallel Prefix AddersSoumya Banerjee, Wenjing Rao. 231-236 [doi]
- On Benchmarking Pin Access for Nanotechnology Standard CellsShang-Rong Fang, Cheng-Wei Tai, Rung-Bin Lin. 237-242 [doi]
- A Power Efficient System Design Methodology Employing Approximate Arithmetic UnitsTuba Ayhan, Firat Kula, Mustafa Altun. 243-248 [doi]
- A Side-Channel Attack Resistant AES with 500Mbps, 1.92pJ/Bit PVT Variation Tolerant True Random Number GeneratorYimai Peng, Haobo Zhao, Xun Sun, Chen Sun. 249-254 [doi]
- Unobtrusive Wearable Health Monitoring SystemAli A. Aboughaly, Mohamed A. Abd El ghany. 255-259 [doi]
- Low Power Image Acquisition Scheme Using On-Pixel Event Driven HalftoningSangamesh Kodge, Himanshu Chaudhary, Mrigank Sharad. 260-265 [doi]
- Low Power Implantable Spike Sorting Scheme Based on Neuromorphic Classifier with Supervised Training EngineRakshit Pathak, Saurav Dash, Anand Kumar Mukhopadhyay, Arindam Basu, Mrigank Sharad. 266-271 [doi]
- A Power Delivery Network and Cell Placement Aware IR-Drop Mitigation Technique: Harvesting Unused Timing Slacks to Schedule Useful SkewsLakshmi Bhamidipati, Bhoopal Gunna, Houman Homayoun, Avesta Sasan. 272-277 [doi]
- Physical Design Variation in Relative Timed Asynchronous CircuitsTannu Sharma, Kenneth S. Stevens. 278-283 [doi]
- Exploiting Bus Communication to Improve Cache Attacks on Systems-on-ChipsJohanna Sepúlveda, Mathieu Gross, Andreas Zankl, Georg Sigl. 284-289 [doi]
- Detection of Layout-Level Trojans by Monitoring Substrate with Preexisting Built-in SensorsLeonel Acunha Guimaraes, Rodrigo Possamai Bastos, Laurent Fesquet. 290-295 [doi]
- Coding for Efficient Caching in Multicore Embedded SystemsTosiron Adegbija, Ravi Tandon. 296-301 [doi]
- A Workload Characterization for the Internet of Medical Things (IoMT)Ankur Limaye, Tosiron Adegbija. 302-307 [doi]
- Functional Broadside Test Generation Using a Commercial ATPG ToolNaixing Wang, Bo Yao, Xijiang Lin, Irith Pomeranz. 308-313 [doi]
- Static Compaction by Merging of Seeds for LFSR-Based Test GenerationIrith Pomeranz. 314-319 [doi]
- Comprehensive Study for Detection of Weak Resistive Open and Short Defects in FDSOI TechnologyAmit Karel, Florence Azaïs, Mariane Comte, Jean Marc Gallière, Michel Renovell, Keshav Singh. 320-325 [doi]
- Offset Analysis and Design Optimization of a Dynamic Sense Amplifier for Resistive MemoriesSalmen Mraihi, El Mehdi Boujamaa, Cyrille Dray, Jacques-Olivier Klein. 326-331 [doi]
- Efficient Metastability-Containing MultiplexersStephan Friedrichs, Attila Kinali. 332-337 [doi]
- Micro Latch-Up Analysis on Ultra-Nanometer VLSI Technologies: A New Monte Carlo ApproachSarah Azimi, Luca Sterpone. 338-343 [doi]
- GREAT: HeteroGeneous IntegRated Magnetic tEchnology Using Multifunctional Standardized sTackMehdi Baradaran Tahoori, Sarath Mohanachandran Nair, Rajendra Bishnoi, Sophiane Senni, Jad Mohdad, Frédérick Mailly, Lionel Torres, Pascal Benoit, Pascal Nouet, Rui Ma, Martin Kreißig, Frank Ellinger, Kotb Jabeur, Pierre Vanhauwaert, Gregory di Pendina, Guillaume Prenat. 344-349 [doi]
- Project HIPNOS: Case Study of High Performance Avionics for Active Debris Removal in SpaceGeorge Lentaris, Ioannis Stratakos, Ioannis Stamoulias, Konstantinos Maragos, Dimitrios Soudris, Manolis I. A. Lourakis, Xenophon Zabulis, David Gonzalez-Arjona. 350-355 [doi]
- Hardware Security for Critical Infrastructures - The CIPSEC Project ApproachApostolos P. Fournaris, Konstantinos Lampropoulos, Odysseas G. Koufopavlou. 356-361 [doi]
- AEGLE's Cloud Infrastructure for Resource Monitoring and Containerized Accelerated AnalyticsKonstantina Koliogeorgi, Dimosthenis Masouros, Georgios Zervakis, Sotirios Xydis, Tobias Becker, Georgi Gaydadjiev, Dimitrios Soudris. 362-367 [doi]
- A CAD Open Platform for High Performance Reconfigurable Systems in the EXTRA ProjectMarco Rabozzi, Rolando Brondolin, Giuseppe Natale, Emanuele Del Sozzo, Michael Hübner, Andreas Brokalakis, Catalin Bogdan Ciobanu, Dirk Stroobandt, Marco Domenico Santambrogio. 368-373 [doi]
- Profile-Driven Power Optimizations for AAL Robots: Maximizing Robots Idle Time by Offloading Monitoring Workload to Dedicated Hardware ComponentsGeorgios Keramidas, Nikolaos S. Voros, Christos P. Antonopoulos, Fynn Schwiegelshohn, Philipp Wehner, Diana Göhringer, Evaggelinos P. Mariatos. 374-378 [doi]
- Unified Model for Contrast Enhancement and DenoisingAlex Pappachen James, Olga Krestinskaya, Joshin John Mathew. 379-384 [doi]
- SDN-Based Circuit-Switching for Many-CoresMarcelo Ruaro, Henrique Martins Medina, Fernando Gehm Moraes. 385-390 [doi]
- NEDA: NOP Exploitation with Dependency Awareness for Reliable VLIW ProcessorsRafail Psiakis, Angeliki Kritikakou, Olivier Sentieys. 391-396 [doi]
- Serial ATA Commands Logger for Security Monitoring on FPGA DevicesDan Cristian Turicu, Octavian Cret, Lucia Vacariu. 397-402 [doi]
- PACT: Priority-Aware Phase-Based Cache Tuning for Embedded SystemsSam Gianelli, Tosiron Adegbija. 403-408 [doi]
- CAPSL: The Component Authentication Process for Sandboxed LayoutsTaylor J. L. Whitaker, Christophe Bobda. 409-414 [doi]
- Formal Verification of Truncated Multipliers Using Algebraic Approach and Re-SynthesisTiankai Su, Cunxi Yu, Atif Yasin, Maciej J. Ciesielski. 415-420 [doi]
- Assessing Self-Repair on FPGAs with Biologically Realistic Astrocyte-Neuron NetworksShvan Karim, Jim Harkin, Liam McDaid, Bryan Gardiner, Junxiu Liu, David M. Halliday, Andy M. Tyrrell, Jon Timmis, Alan G. Millard, Anju P. Johnson. 421-426 [doi]
- Memristor-Based Clock Design and Optimization with In-Situ TunabilityShuyu Kong, Jie Gu, Hai Zhou. 427-432 [doi]
- Reconfigurable Hardened Latch and Flip-Flop for FPGAsHamzeh Ahangari, Ihsen Alouani, Özcan Özturk, Smaïl Niar. 433-438 [doi]
- Efficient Reconfigurable Global Network-on-Chip Designs towards Heterogeneous CPU-GPU Systems: An Application-Aware ApproachTung Thanh Le, Dan Zhao, Magdy Bayoumi. 439-444 [doi]
- Parallel Simulation-Based Verification of RC Power GridsMohammad Fawaz, Farid N. Najm. 445-452 [doi]
- An Effective Power Grid Optimization Approach for the Electromigration ReliabilityMing Yan, Yici Cai, Chenguang Wang, Qiang Zhou. 453-458 [doi]
- On Tolerating Faults of TSV/Microbumps for Power Delivery Networks in 3D ICSheng-Hsin Fang, Chang-Tzu Lin, Wei-Hsun Liao, Chien-Chia Huang, Li-Chin Chen, Hung-Ming Chen, I-Hsuan Lee, Ding-Ming Kwai, Yung-Fa Chou. 459-464 [doi]
- WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTSScott Lerner, Baris Taskin. 465-470 [doi]
- Automatic Assertion Generation for Simulation, Formal Verification and EmulationTong Zhang, Daniel G. Saab, Jacob A. Abraham. 471-476 [doi]
- Cache Partitioning + Loop Tiling: A Methodology for Effective Shared Cache ManagementVasilios I. Kelefouras, Georgios Keramidas, Nikolaos S. Voros. 477-482 [doi]
- OFDM Based High Data Rate, Fading Resilient Transceiver for Wireless Networks-on-ChipSri Harsha Gade, Sakshi Garg, Sujay Deb. 483-488 [doi]
- DENA: A DVFS-Capable Heterogeneous NoC ArchitectureLuca Cremona, William Fornaciari, Andrea Marchese, Michele Zanella, Davide Zoni. 489-494 [doi]
- Exploiting Configurability as a Defense against Cache Side Channel AttacksChenxi Dai, Tosiron Adegbija. 495-500 [doi]
- CCATDC: A Configurable Compact Algorithmic Time-to-Digital ConverterShuo Li, Xiaolin Xu, Wayne Burleson. 501-506 [doi]
- AIsim: Functional Simulator for Analog-to-Information Perceptual SystemsHong Liu, Zheyu Liu, Fei Qiao, Mark Po-Hung Lin, Qi Wei, Huazhong Yang. 507-512 [doi]
- A Hierarchical and Programmable OTA-C FilterMousumi Bhanja, Baidyanath Ray. 513-518 [doi]
- A 0.3V Low Cost Low Power 24 GHz Low Noise Amplifier with Body Bias TechnologyMing-Yu Huang, Ren-Yuan Huang, Ro-Min Weng. 519-522 [doi]
- Capacitor Mismatch Calibration Technique to Improve the SFDR of 14-Bit SAR ADCHua Fan, Franco Maloberti, Dagang Li, Daqian Hu, Yuanjun Cen, Hadi Heidari. 523-528 [doi]
- Design of an Asynchronous Detector with Priority Encoding TechniqueKeunyeol Park, Ohoon Kwon, Hyunseob Noh, Minhyun Jin, Minkyu Song. 529-532 [doi]
- Towards Making Fault Injection on Abstract Models a More Accurate Tool for Predicting RT-Level EffectsTino Flenker, Jan Malburg, Görschwin Fey, Serhiy Avramenko, Massimo Violante, Matteo Sonza Reorda. 533-538 [doi]
- Transistor Temperature Deviation Analysis in Monolithic 3D Standard CellsMelanie Brocard, Benoît Mathieu, Jean-Philippe Colonna, Cristiano Santos, Claire Fenouillet-Béranger, Cao-Minh Vincent Lu, Gerald Cibrario, Laurent Brunet, Perrine Batude, François Andrieu, Sebastien Thuries, Olivier Billoint. 539-544 [doi]
- Reducing Search Space for Fault Diagnosis: A Probability-Based Scoring ApproachHossein Sabaghian Bidgoli, Payman Behnam, Bijan Alizadeh, Zainalabedin Navabi. 545-550 [doi]
- Layout Vulnerability Reduction against Trojan Insertion Using Security-Aware White Space DistributionHamed Hossein-Talaee, Ali Jahanian. 551-555 [doi]
- Semiformal Verification of Software-Controlled ConnectionsTomas Grimm, Djones Lettnin, Michael Hübner. 556-561 [doi]
- Compact Modeling of Graphene Barristor for Digital Integrated Circuit DesignZhou Zhao, Xinlu Chen, Ashok Srivastava, Lu Peng, Saraju P. Mohanty. 562-567 [doi]
- Performing Mathematics Using DNA: Complex Number Arithmetic Using Sticker ModelMayukh Sarkar, Prasun Ghosal. 568-573 [doi]
- Analysis of Side-Channel Attack AES Hardware Trojan Benchmarks against CountermeasuresSudeendra Kumar K, Sauvagya Ranjan Sahoo, Abhishek Mahapatra, Ayas Kanta Swain, K. K. Mahapatra. 574-579 [doi]
- A VCO-Based MPPT Circuit for Low-Voltage Energy HarvestersAli H. Hassan, Esraa M. Hamed, Eman Badr, Omar Elsharqawy, Tawfik Ismail, S. R. I. Gabran, Yehea Ismail, Hassan Mostafa. 580-584 [doi]
- Design of 5-Bit Flash ADC Using Multiple Input Standard Cell Gates for Large Input SwingSumit Khalapure, R. K. Siddharth, Kumar Y. B. Nithin, M. H. Vasantha. 585-588 [doi]
- A 0.5 V Low Power OTA-C Low Pass Filter for ECG DetectionRakhi R., Abhijeet D. Taralkar, M. H. Vasantha, Kumar Y. B. Nithin. 589-593 [doi]
- A Novel Opamp and Capacitor Sharing 10 Bit 20 MS/s Low Power Pipelined ADC in 0.18µm CMOS TechnologyGreeshma R, Anoop V. K, B. Venkataramani. 594-599 [doi]
- Design of Low Power 4-Bit 400MS/s Standard Cell Based Flash ADCS. M. Mayur, R. K. Siddharth, Kumar Y. B. Nithin, M. H. Vasantha. 600-603 [doi]
- A Novel CMOS-Based Fully Differential Operational Floating ConveyorHossam ElGemmazy, Amr Helmy, Hassan Mostafa, Yehea Ismail. 604-608 [doi]
- Dopingless Transistor Based Hybrid Oscillator Arbiter Physical Unclonable FunctionVenkata P. Yanambaka, Saraju P. Mohanty, Elias Kougianos, Prabha Sundaravadivel, Jawar Singh. 609-614 [doi]
- Exploiting Memristive Crossbar Memories as Dual-Use Security Primitives in IoT DevicesGarrett S. Rose, Md. Badruddoja Majumder, Mesbah Uddin. 615-620 [doi]
- Adiabatic Computing Based Low-Power and DPA-Resistant Lightweight Cryptography for IoT DevicesHimanshu Thapliyal, T. S. S. Varun, S. Dinesh Kumar. 621-626 [doi]
- Adaptive and Energy-Efficient Architectures for Machine Learning: Challenges, Opportunities, and Research RoadmapMuhammad Shafique, Rehan Hafiz, Muhammad Usama Javed, Sarmad Abbas, Lukás Sekanina, Zdenek Vasícek, Vojtech Mrazek. 627-632 [doi]
- Data Stream Processing in Networks-on-ChipJens Rettkowski, Diana Göhringer. 633-638 [doi]
- On How to Design Dataflow FPGA-Based Accelerators for Convolutional Neural NetworksGiuseppe Natale, Marco Bacis, Marco Domenico Santambrogio. 639-644 [doi]
- Hardware Acceleration for Machine LearningRuizhe Zhao, Wayne Luk, Xinyu Niu, Huifeng Shi, Haitao Wang. 645-650 [doi]
- A Fully Integrated Fast-Response LDO Voltage Regulator with Adaptive Transient Current DistributionXingyuan Tong, Kangkang Wei. 651-654 [doi]
- A 0.32 µW, 76.8 dB SNDR Programmable Gain Instrumentation Amplifier for Bio-Potential Signal Processing ApplicationsMahesh Kumar Adimulam, Krishna Kumar Movva, K. Kolluru, M. B. Srinivas. 655-660 [doi]
- A Digital Offset Reduction Method for Dynamic Comparators Based on Phase MeasurementAndres Amaya, Javier Ardila, Elkim Roa. 661-664 [doi]
- Reconfigurable Robust Hybrid Oscillator Arbiter PUF for IoT Security Based on DL-FETVenkata P. Yanambaka, Saraju P. Mohanty, Elias Kougianos, Prabha Sundaravadivel, Jawar Singh. 665-670 [doi]
- An IoT Enabled Real-Time Communication and Location Tracking System for Vehicular EmergencySubha Koley, Prasun Ghosal. 671-676 [doi]
- A Flexible Pay-per-Device Licensing Scheme for FPGA IP CoresK. Sudeendra Kumar, Sauvagya Ranjan Sahoo, Abhishek Mahapatra, Ayas Kanta Swain, K. K. Mahapatra. 677-682 [doi]
- In-Memory Computing with Spintronic DevicesDeliang Fan, Shaahin Angizi, Zhezhi He. 683-688 [doi]
- Approximate SRAM for Energy-Efficient, Privacy-Preserving Convolutional Neural NetworksLita Yang, Boris Murmann. 689-694 [doi]