Table of Contents

• SafeTPU: A Verifiably Secure Hardware Accelerator for Deep Neural NetworksMaria I. Mera Collantes, Zahra Ghodsi, Siddharth Garg. 1-6 [doi]
• Low-Power Weighted Pseudo-Random Test Pattern Generation for Launch-on-Capture Delay TestingDong Xiang, Jiaming Cai, Bo Liu. 1-6 [doi]
• Pinhole Latent Defect Modeling and Simulation for Defect-Oriented Analog/Mixed-Signal TestingJhon Gomez, Nektar Xama, Anthony Coyette, Ronny Vanhooren, Wim Dobbelaere, Georges G. E. Gielen. 1-6 [doi]
• Special Session: Physically Flexible Devices for Health and Activity Monitoring: Challenges from Design to TestYigit Tuncel, Ganapati Bhat, Ümit Y. Ogras. 1-5 [doi]
• Reliability Evaluation of Turbo Decoders Implemented on SRAM-FPGAsZhen Gao, Lingling Zhang, Ruishi Han, Pedro Reviriego, Zhiqiang Li. 1-6 [doi]
• A Zero-Cost Detection Approach for Recycled ICs using Scan ArchitectureWendong Wang, Ujjwal Guin, Adit D. Singh. 1-6 [doi]
• Special Session: Survey of Test Point Insertion for Logic Built-in Self-testYang Sun, Spencer K. Millican, Vishwani D. Agrawal. 1-6 [doi]
• Switch Level Time Simulation of CMOS Circuits with Adaptive Voltage and Frequency ScalingEric Schneider, Hans-Joachim Wunderlich. 1-6 [doi]
• Flush+Time: A High Accuracy and High Resolution Cache Attack On ARM-FPGA Embedded SoCChuran Tang, Pengkun Liu, Cunqing Ma, Zongbin Liu, Jingquan Ge. 1-6 [doi]
• Selective Checksum based On-line Error Correction for RRAM based Matrix OperationsAbhishek Das, Nur A. Touba. 1-6 [doi]
• Special Session: Test Challenges in a Chiplet MarketplaceM. Hutner, R. Sethuram, B. Vinnakota, D. Armstrong, A. Copperhall. 1-12 [doi]
• Aging-resilient SRAM design: an end-to-end frameworkXuan Zuo, Sandeep K. Gupta. 1-6 [doi]
• CNN-based Stochastic Regression for IDDQ Outlier IdentificationChun-Teng Chen, Chia-Heng Yen, Cheng-Yen Wen, Cheng-Hao Yang, Kai-Chiang Wu, Mason Chern, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Shu-Yi Kao, Mango Chia-Tso Chao. 1-6 [doi]
• LSTM-based Analysis of Temporally- and Spatially-Correlated Signatures for Intermittent Fault DetectionXingyi Wang, Li Jiang 0002, Krishnendu Chakrabarty. 1-6 [doi]
• Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous CircuitsBrett Sparkman, Scott C. Smith, Jia Di. 1-6 [doi]
• Ultra-Wideband Modulation Signal Measurement Using Local Sweep Digitizing MethodKoji Asami, Keisuke Kusunoki, Nobuhiro Shimizu, Yoshiyuki Aoki. 1-6 [doi]
• A dynamic reconfiguration mechanism to increase the reliability of GPGPUsJosie E. Rodriguez Condia, Pierpaolo Narducci, Matteo Sonza Reorda, Luca Sterpone. 1-6 [doi]
• SNIFU: Secure Network Interception for Firmware Updates in legacy PLCsHadjer Benkraouda, Muhammad Ashif Chakkantakath, Anastasis Keliris, Michail Maniatakos. 1-6 [doi]
• Taming Combinational Trojan Detection Challenges with Self-Referencing Adaptive Test PatternsChris Nigh, Alex Orailoglu. 1-6 [doi]
• ATTEST: Application-Agnostic Testing of a Novel Transistor-Level Programmable FabricMustafa Munawar Shihab, Bharath Ramanidharan, Suraag Sunil Tellakula, Gaurav Rajavendra Reddy, Jingxiang Tian, Carl Sechen, Yiorgos Makris. 1-6 [doi]
• A Deterministic-Statistical Multiple-Defect Diagnosis MethodologySoumya Mittal, R. D. Shawn Blanton. 1-6 [doi]
• Innovative Practice on Wafer Test InnovationsDyi-Chung Hu, Hirohito Hashimoto, Li-Fong Tseng, Ken Chau-Cheung Cheng, Katherine Shu-Min Li, Sying-Jyan Wang, Sean Y.-S. Chen, Jwu E. Chen, Clark Liu, Andrew Yi-Ann Huang. 1 [doi]
• Special Session: The Recent Advance in Hardware Implementation of Post-Quantum CryptographyJiafeng Xie, Kanad Basu, Kris Gaj, Ujjwal Guin. 1-10 [doi]
• A New Secure Scan Design with PUF-based Key for AuthenticationQidong Wang, Aijiao Cui, Gang Qu, Huawei Li. 1-6 [doi]
• Special Session: AutoSoC - A Suite of Open-Source Automotive SoC BenchmarksFelipe Augusto da Silva, Ahmet Cagri Bagbaba, Annachiara Ruospo, Riccardo Mariani, Ghani Kanawati, Ernesto Sánchez 0001, Matteo Sonza Reorda, Maksim Jenihhin, Said Hamdioui, Christian Sauer 0001. 1-9 [doi]
• In-field Functional Test of CAN Bus ControllersRiccardo Cantoro, Sandro Sartoni, Matteo Sonza Reorda. 1-6 [doi]
• DFSSD: Deep Faults and Shallow State Duality, A Provably Strong Obfuscation Solution for Circuits with Restricted Access to Scan ChainShervin Roshanisefat, Hadi Mardani Kamali, Kimia Zamiri Azar, Sai Manoj Pudukotai Dinakarrao, Naghmeh Karimi, Houman Homayoun, Avesta Sasan. 1-6 [doi]
• Sequence Triggered Hardware Trojan in Neural Network AcceleratorZizhen Liu, Jing Ye, Xing Hu, Huawei Li, Xiaowei Li 0001, Yu Hu. 1-6 [doi]
• Mitigating Read Failures in STT-MRAMSarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori. 1-6 [doi]
• Non-Masking Non-Robust Tests for Path Delay FaultsIrith Pomeranz. 1-6 [doi]
• Effective Design of Layout-Friendly EDT DecompressorYu Huang, Janusz Rajski, Mark Kassab, Nilanjan Mukherjee 0001, Jeffrey Mayer. 1-6 [doi]
• Internal I/O Testing: Definition and a SolutionSreejit Chakravarty, Fei Su, Indira A. Gohad, Sudheer V. Bandana, B. S. Adithya, Wei Ming Lim. 1-6 [doi]
• SeRFI: Secure Remote FPGA Initialization in an Untrusted EnvironmentAdam Duncan, Adib Nahiyan, Fahim Rahman, Grant Skipper, Martin Swany, Andrew Lukefahr, Farimah Farahmandi, Mark Tehranipoor. 1-6 [doi]
• Special Session: Novel Attacks on Logic-LockingAyush Jain, Ujjwal Guin, M. Tanjidur Rahman, Navid Asadizanjani, Danielle Duvalsaint, R. D. Shawn Blanton. 1-10 [doi]
• Dynamic Multi-Frequency Test Method for Hidden Interconnect DefectsSomayeh Sadeghi Kohan, Sybille Hellebrand. 1-6 [doi]
• Automated Design For Yield Through Defect ToleranceSuriyaprakash Natarajan, Andres F. Malavasi, Pascal Andreas Meinerzhagen. 1-6 [doi]
• Quantile - Quantile Fitting Approach to Detect Site to Site Variations in Massive Multi-site TestingPraise O. Farayola, Shravan K. Chaganti, Abdullah O. Obaidi, Abalhassan Sheikh, Srivaths Ravi 0001, Degang Chen. 1-6 [doi]
• On Classification of Acceptable Images for Reliable Artificial Intelligence Systems: A Case Study on Pedestrian DetectionTong-Yu Hsieh, Pin-Xuan Wu, Chun-Chao Cheng. 1-6 [doi]
• Special Session - Emerging Memristor Based Memory and CIM Architecture: Test, Repair and Yield AnalysisRajendra Bishnoi, Lizhou Wu, Moritz Fieback, Christopher Münch, Sarath Mohanachandran Nair, Mehdi Baradaran Tahoori, Ying Wang, Huawei Li, Said Hamdioui. 1-10 [doi]
• ESL, Back-annotating Crosstalk Fault Models into High-level Communication LinksKatayoon Basharkhah, Rezgar Sadeghi, Nooshin Nosrati, Zainalabedin Navabi. 1-6 [doi]
• Input Test Data Volume Reduction Using Seed Complementation and Multiple LFSRsIrith Pomeranz. 1-6 [doi]
• Innovative Test Practices in AsiaTakeshi Iwasaki, Masao Aso, Haruji Futami, Satoshi Matsunaga, Yousuke Miyake, Takaaki Kato, Seiji Kajihara, Yukiya Miura, Smith Lai, Gavin Hung, Harry H. Chen, Haruo Kobayashi 0001, Kazumi Hatayama. 1 [doi]
• Co-Optimization of Grid-Based TAM Wire Routing and Test Scheduling with Reconfigurable WrappersJui-Hung Hung, Shih-Hsu Huang, Chun-Hua Cheng, Hsu-Yu Kao, Wei-Kai Cheng. 1-6 [doi]