Abstract is missing.
- Tutorial-1: Machine learning and deep learningJinjun Xiong. [doi]
- Keynote I: "Designing heterogeneous systems in the AI era: Challenges and opportunities"Jeff Burns. [doi]
- Quantized deep neural networks for energy efficient hardware-based inferenceRuizhou Ding, Zeye Dexter Liu, R. D. (Shawn) Blanton, Diana Marculescu. 1-8 [doi]
- Intelligent corner synthesis via cycle-consistent generative adversarial networks for efficient validation of autonomous driving systemsHandi Yu, Xin Li. 9-15 [doi]
- Deep Learning for Better Variant Calling for Cancer Diagnosis and TreatmentAnand Ramachandran, Huiren Li, Eric Klee, Steven S. Lumetta, Deming Chen. 16-21 [doi]
- Multi-device collaborative management through knowledge sharingZhongyuan Tian, Zhe Wang, Haoran Li, Peng Yang, Rafael Kioji Vivas Maeda, Jiang Xu. 22-27 [doi]
- SQLiteKV: An efficient LSM-tree-based SQLite-like database engine for mobile devicesYuanjing Shi, Zhaoyan Shen, Zili Shao. 28-33 [doi]
- DI-SSD: Desymmetrized interconnection architecture and dynamic timing calibration for solid-state drivesJian-Hao Huang, Ren-Shuo Liu. 34-39 [doi]
- Sound valve-control for programmable microfluidic devicesAndreas Grimmer, Berislav Klepic, Tsung-Yi Ho, Robert Wille. 40-45 [doi]
- Multi-level droplet routing in active-matrix based digital-microfluidic biochipsGuan-Ruei Lu, Bhargab B. Bhattacharya, Tsung-Yi Ho, Hung-Ming Chen. 46-51 [doi]
- MESGA: An MPSoC based embedded system solution for short read genome alignmentVikkitharan Gnanasambandapillai, Arash Bayat, Sri Parameswaran. 52-57 [doi]
- Scheduling and shaping of complex task activations for mixed-criticality systemsBiao Hu, Kai Huang 0002. 58-63 [doi]
- BUQS: Battery- and user-aware QoS scaling for interactive mobile devicesWooseok Lee, Reena Panda, Dam Sunwoo, Jose Joao, Andreas Gerstlauer, Lizy K. John. 64-69 [doi]
- Power conversion efficiency-aware mapping of multithreaded applications on heterogeneous architectures: A comprehensive parameter tuningHossein Sayadi, Divya Pathak, Ioannis Savidis, Houman Homayoun. 70-75 [doi]
- Effect of aging on linear and nonlinear MUX PUFs by statistical modelingAnoop Koyily, Satya Venkata Sandeep Avvaru, Chen Zhou, Chris H. Kim, Keshab K. Parhi. 76-83 [doi]
- ASAX: Automatic security assertion extraction for detecting Hardware TrojansChenguang Wang, Yici Cai, Qiang Zhou, Haoyi Wang. 84-89 [doi]
- Polymorphic gate based IC watermarking techniquesTian Wang, Xiaoxin Cui, Dunshan Yu, Omid Aramoon, Timothy Dunlap, Gang Qu, Xiaole Cui. 90-96 [doi]
- A machine learning attack resistant multi-PUF design on FPGAQingqing Ma, Chongyan Gu, Neil Hanley, Chenghua Wang, Weiqiang Liu, Máire O'Neill. 97-104 [doi]
- Supporting compressed-sparse activations and weights on SIMD-like accelerator for sparse convolutional neural networksChien-Yu Lin, Bo-Cheng Lai. 105-110 [doi]
- IMCE: Energy-efficient bit-wise in-memory convolution engine for deep neural networkShaahin Angizi, Zhezhi He, Farhana Parveen, Deliang Fan. 111-116 [doi]
- Training low bitwidth convolutional neural network on RRAMYi Cai, Tianqi Tang, Lixue Xia, Ming Cheng, Zhenhua Zhu, Yu Wang, Huazhong Yang. 117-122 [doi]
- A high-throughput and energy-efficient RRAM-based convolutional neural network using data encoding and dynamic quantizationXizi Chen, Jingbo Jiang, Jingyang Zhu, Chi-Ying Tsui. 123-128 [doi]
- DRL-cloud: Deep reinforcement learning-based resource provisioning and task scheduling for cloud service providersMingxi Cheng, Ji Li, Shahin Nazarian. 129-134 [doi]
- Pairing of microring-based silicon photonic transceivers for tuning power optimizationRui Wu, M. Ashkan Seyedi, Yuyang Wang, Jared Hulme, Marco Fiorentino, Raymond G. Beausoleil, Kwang-Ting Cheng. 135-140 [doi]
- Neu-NoC: A high-efficient interconnection network for accelerated neuromorphic systemsXiaoxiao Liu, Wei Wen, Xuehai Qian, Hai Li, Yiran Chen. 141-146 [doi]
- A lifetime-aware mapping algorithm to extend MTTF of Networks-on-ChipLetian Huang, Shuyu Chen, Qiong Wu, Masoumeh Ebrahimi, Junshi Wang, Shuyan Jiang, Qiang Li. 147-152 [doi]
- Layout-dependent aging mitigation for critical path timingChe-Lun Hsu, Shaofeng Guo, Yibo Lin, Xiaoqing Xu, Meng Li, Runsheng Wang, Ru Huang, David Z. Pan. 153-158 [doi]
- MTTF-aware design methodology of error prediction based adaptively voltage-scaled circuitsYutaka Masuda, Masanori Hashimoto. 159-165 [doi]
- A highly compressed timing macro-modeling algorithm for hierarchical and incremental timing analysisTin-Yin Lai, Martin D. F. Wong. 166-171 [doi]
- FastPass: Fast timing path search for generalized timing exception handlingPei-Yu Lee, Iris Hui-Ru Jiang, Tung-Chieh Chen. 172-177 [doi]
- ReGAN: A pipelined ReRAM-based accelerator for generative adversarial networksFan Chen, Linghao Song, Yiran Chen. 178-183 [doi]
- Quad-multiplier packing based on customized floating point for convolutional neural networks on FPGAZhifeng Zhang, Dajiang Zhou, Shihao Wang, Shinji Kimura. 184-189 [doi]
- Sparse ternary connect: Convolutional neural networks using ternarized weights with enhanced sparsityCanran Jin, Heming Sun, Shinji Kimura. 190-195 [doi]
- A deep reinforcement learning framework for optimizing fuel economy of hybrid electric vehiclesPu Zhao, Yanzhi Wang, Naehyuck Chang, Qi Zhu, Xue Lin. 196-202 [doi]
- Process variation and temperature aware adaptive scrubbing for retention failures in STT-MRAMNour Sayed, Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori. 203-208 [doi]
- PIMCH: Cooperative memory prefetching in processing-in-memory architectureSheng Xu, Ying Wang, Yinhe Han, Xiaowei Li. 209-214 [doi]
- CAMO: A novel cache management organization for GPGPUsDebiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam, Laxmi Narayan Bhuyan. 215-220 [doi]
- Process variation aware data management for magnetic skyrmions racetrack memoryFan Chen, Zheng Li, Wang Kang, Weisheng Zhao, Hai Li, Yiran Chen. 221-226 [doi]
- Optimizing dynamic mapping techniques for on-line NoC testShuyan Jiang, Qiong Wu, Shuyu Chen, Junshi Wang, Masoumeh Ebrahimi, Letian Huang, Qiang Li. 227-232 [doi]
- On enabling diagnosis for 1-Pin Test fails in an industrial flowDaniel Tille, Benedikt Gottinger, Ulrike Pfannkuchen, Helmut Graeb, Ulf Schlichtmann. 233-238 [doi]
- Approximation-aware testing for approximate circuitsArun Chandrasekharan, Stephan Eggersglüß, Daniel Große, Rolf Drechsler. 239-244 [doi]
- A channel-sharable built-in self-test scheme for multi-channel DRAMsKuan-Te Wu, Jin-Fu Li, Chih-Yen Lo, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou. 245-250 [doi]
- Concerted wire lifting: Enabling secure and cost-effective split manufacturingSatwik Patnaik, Johann Knechtel, Mohammed Ashraf, Ozgur Sinanoglu. 251-258 [doi]
- A conflict-free approach for parallelizing SAT-based de-camouflaging attacksXueyan Wang, Qiang Zhou, Yici Cai, Gang Qu. 259-264 [doi]
- A practical split manufacturing framework for Trojan prevention via simultaneous wire lifting and cell insertionMeng Li 0004, Bei Yu 0001, Yibo Lin, Xiaoqing Xu, Wuxi Li, David Z. Pan. 265-270 [doi]
- A comparative investigation of approximate attacks on logic encryptionsYuanqi Shen, Amin Rezaei, Hai Zhou. 271-276 [doi]
- An ultra-low-noise differential relaxation oscillator based on a swing-boosting schemeJunghyup Lee, Arup K. George, Minkyu Je. 277-278 [doi]
- A nonvolatile flip-flop-enabled cryptographic wireless authentication tag with per-query key update and power-glitch attack countermeasuresChiraag Juvekar, Anantha P. Chandrakasan, Joyce Kwong, Hyung-Min Lee. 279-280 [doi]
- A 42nJ/conversion on-demand state-of-charge indicator for miniature IoT Li-ion batteriesJunwon Jeong, Seokhyeon Jeong, Chulwoo Kim, Dennis Sylvester, David Blaauw. 281-282 [doi]
- A supply noise insensitive PLL with a rail-to-rail swing ring oscillator and a wideband noise suppression loopDongin Kim, SeongHwan Cho. 283-284 [doi]
- A dual-output SC converter with dynamic power allocation for multicore application processorsJunmin Jiang, Yan Lu 0002, Xun Liu, Wing-Hung Ki, Philip K. T. Mok, Seng-Pan U, Rui P. Martins. 285-286 [doi]
- 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interfaceYeonho Lee, Yoonjae Choi, Chulwoo Kim. 287-288 [doi]
- A digital SC converter with high efficiency and low voltage rippleJunmin Jiang, Wing-Hung Ki, Yan Lu 0002. 289-290 [doi]
- A reconfigurable SIMO system with 10-output dual-bus DC-DC converter using the load balancing function in group allocator for diversified load conditionSe-un Shin, Sang-Hui Park, Gyu-Hyeong Cho. 291-292 [doi]
- Real-time depth map processor for offset aperture based single camera systemHyeji Kim, Jinyeon Lim, Yeongmin Lee, Woojin Yun, Young-Gyu Kim, Wonseok Choi, Asim Khan, Muhammad Umar Karim Khan, Said Homidov, Hyun-Sang Park, Chong-Min Kyung. 293-294 [doi]
- Edge pursuit comparator with application in a 74.1dB SNDR, 20KS/s 15b SAR ADCMinseob Shim, Seokhyeon Jeong, Paul D. Myers, Suyoung Bang, Junhua Shen, Chulwoo Kim, Dennis Sylvester, David Blaauw, Wanyeong Jung. 295-296 [doi]
- A 300-pW audio ΑΣ modulator with 100.5-dB DR using dynamic bias inverterSangwoo Lee, Woojin Jo, Seung-Woo Song, Youngcheol Chae. 297-298 [doi]
- An external-capacitor-less high-PSR low-dropout regulator using an adaptive supply-ripple cancellation technique to the body-gateYounghyun Lim, Jeonghyun Lee, Suneui Park, Jaehyouk Choi. 299-300 [doi]
- A 230-260GHz wideband amplifier in 65nm CMOS based on dual-peak Gmax-coreDae-Woong Park, Dzuhri Radityo Utomo, Jong-Phil Hong, Sang-Gug Lee. 301-302 [doi]
- Injection-locked frequency multiplier with a continuous frequency-tracking loop for 5G transceiversSeyeon Yoo, Seojin Choi, Juyeop Kim, Heein Yoon, Yongsun Lee, Jaehyouk Choi. 303-304 [doi]
- A 6.9mW 120fps 28×50 capacitive touch sensor for 1mm-φ stylus using current-driven ΔΣ ADCsHyunseok Hwang, Hyeyeon Lee, Youngcheol Chae. 305-306 [doi]
- A switched-loop-filter PLL with fast phase-error correction techniqueYongsun Lee, Taeho Seong, Seyeon Yoo, Jaehyouk Choi. 307-308 [doi]
- A 9.3 nW all-in-one bandgap voltage and current reference circuit using leakage-based PTAT generation and DIBL characteristicYoungwoo Ji, Cheonhoo Jeon, Hyunwoo Son, Byungsub Kim, Hong June Park, Jae-Yoon Sim. 309-310 [doi]
- A 16.6-pJ/b 150-Mb/s body-channel communication transceiver with decision feedback equalization improving >200x area efficiencyJi Hoon Lee, Kwangmin Kim, Minsoo Choi, Jae-Yoon Sim, Hong June Park, Byungsub Kim. 311-312 [doi]
- Low power FSK transceiver using ADPLL with direct modulation and integrated SPDT for BLE applicationDong Soo Lee, Sungjin Kim, SeongJin Oh, Gyusub Won, Thi Kim Nga Truong, Imran Ali, Hamed Abbasizadeh, Behnam Samadpoor Rikan, Kang-Yoon Lee. 313-314 [doi]
- A 2.22 Gbps high-throughput NB-LDPC decoder in 65nm CMOS with aggressive overlap schedulingInjun Choi, Ji-Hoon Kim. 315-316 [doi]
- Design of resource sharing reconfigurable ΔΣ SAR-ADCMotomi Ishizuka, Kohei Yamada, Hiroki Ishikuro. 317-318 [doi]
- A 2.4GHz, -102dBm-sensitivity, 25kb/s, 0.466mW interference resistant BFSK multi-channel sliding-IF ULP receiverOh-Yong Jung, Hyun-Gi Seok, Anjana Dissanayake, Sang-Gug Lee. 319-320 [doi]
- Highly sensitive fingerprint readout IC for glass-covered mutual capacitive fingerprint sensorKyeong-min Park, Joohyeb Song, Franklin Bien. 321-322 [doi]
- A 5.8 GHz DSRC digitally controlled CMOS RF-SoC transceiver for China ETCHuimin Liu, Xiongfei Qu, Lingling Cao, Ruifeng Liu, Yuanzhi Zhang, Meijuan Zhang, Xiaoqiang Li, Wenshen Wang, Chao Lu. 323-324 [doi]
- A low-power wide dynamic-range current readout circuit for biosensorsHyunwoo Son, Hwasuk Cho, Jahyun Koo, Youngwoo Ji, Byungsub Kim, Hong June Park, Jae-Yoon Sim. 325-326 [doi]
- An efficient fixed-point arithmetic processor using a hybrid CORDIC algorithmHong-Thu Nguyen, Xuan-Thuan Nguyen, Cong-Kha Pham. 327-328 [doi]
- A 2.4pJ/bit, 6.37Gb/s SPC-enhanced BC-BCH decoder in 65nm CMOS for NAND flash storage systemsJaehwan Jung, In-Cheol Park, Youngjoo Lee. 329-330 [doi]
- Exploring energy and accuracy tradeoff in structure simplification of trained deep neural networksBoyu Zhang, Azadeh Davoodi, Yu Hen Hu. 331-336 [doi]
- Low latency parallel implementation of traditionally-called stochastic circuits using deterministic shuffling networksZhiheng Wang 0002, Soheil Mohajer, Kia Bazargan. 337-342 [doi]
- Optimizing FPGA-based convolutional neural networks accelerator for image super-resolutionJung-Woo Chang, Suk-Ju Kang. 343-348 [doi]
- XORiM: A case of in-memory bit-comparator implementation and its performance implicationsKaiwei Zou, Ying Wang, Huawei Li, Xiaowei Li. 349-354 [doi]
- Logic synthesis for energy-efficient photonic integrated circuitsZheng Zhao, Zheng Wang, Zhoufeng Ying, Shounak Dhar, Ray T. Chen, David Z. Pan. 355-360 [doi]
- HielM: Highly flexible in-memory computing using STT MRAMFarhana Parveen, Zhezhi He, Shaahin Angizi, Deliang Fan. 361-366 [doi]
- Performance analysis on structure of racetrack memoryHongbin Zhang, Chao Zhang, Qingda Hu, Chengmo Yang, Jiwu Shu. 367-374 [doi]
- Modeling of biaxial magnetic tunneling junction for multi-level cell STT-RAM realizationEnes Eken, Ismail Bayram, Hai Helen Li, Yiran Chen. 375-380 [doi]
- Automatic insertion of airgap with design rule constraintsDaijoon Hyun, Youngsoo Shin. 381-386 [doi]
- On coloring rectangular and diagonal grid graphs for multiple patterning lithographyDaifeng Guo, Hongbo Zhang, Martin D. F. Wong. 387-392 [doi]
- Lifetime-aware design methodology for dynamic partially reconfigurable systemsSiva Satyendra Sahoo, Tuan D. A. Nguyen, Bharadwaj Veeravalli, Akash Kumar 0001. 393-398 [doi]
- Electromigration-lifetime constrained power grid optimization considering multi-segment interconnect wiresHan Zhou, Yijing Sun, Zeyu Sun, Hengyang Zhao, Sheldon X.-D. Tan. 399-404 [doi]
- New directions for learning-based IC design tools and methodologiesAndrew B. Kahng. 405-410 [doi]
- Machine learning and systems for building the next generation of EDA toolsManish Pandey. 411-415 [doi]
- Machine learning based generic violation waiver system with application on electromigration sign-offNorman Chang, Ajay Baranwal, Hao Zhuang, Ming-Chih Shih, Rahul Rajan, Yaowei Jia, Hui-Lun Liao, Ying Shiun Li, Ting Ku, Rex Lin. 416-421 [doi]
- Machine learning for engineeringJeff Dyck. 422-427 [doi]
- Large-scale short-term urban taxi demand forecasting using deep learningSiyu Liao, Liutong Zhou, Xuan Di, Bo Yuan, Jinjun Xiong. 428-433 [doi]
- Utilizing quad-trees for efficient design space exploration with partial assignment evaluationKai Neubauer, Christian Haubelt, Philipp Wanko, Torsten Schaub. 434-439 [doi]
- SCBench: A benchmark design suite for SystemC verification and validationBin Lin, Fei Xie. 440-445 [doi]
- MemFlow: Memory-driven data scheduling with datapath co-design in accelerators for large-scale inference applicationsQi Nie, Sharad Malik. 446-451 [doi]
- A mapping approach between IR and binary CFGs dealing with aggressive compiler optimizations for performance estimationOmayma Matoussi, Frédéric Pétrot. 452-457 [doi]
- System level performance analysis and optimization for the adaptive clocking based multi-core processorByung-Su Kim, Joon-Sung Yang. 458-463 [doi]
- Detecting non-functional circuit activity in SoC designsDustin Peterson, Yannick Boekle, Oliver Bringmann. 464-469 [doi]
- Multi-level timing simulation on GPUsEric Schneider, Michael A. Kochte, Hans-Joachim Wunderlich. 470-475 [doi]
- An optimal gate design for the synthesis of ternary logic circuitsSunmean Kim, Taeho Lim, Seokhyeong Kang. 476-481 [doi]
- Performance-preserved analog routing methodology via wire load reductionHao-Yu Chi, Hwa-Yi Tseng, Chien-Nan Jimmy Liu, Hung-Ming Chen. 482-487 [doi]
- Static timing analysis for ring oscillatorsDavid M. Moore, Jeffrey A. Fredenburgh, Muhammad Faisal, David D. Wentzloff. 488-493 [doi]
- OCV guided clock tree topology reconstructionNecati Uysal, Rickard Ewetz. 494-499 [doi]
- Cohesive techniques for cell layout optimization supporting 2D metal-1 routing completionKyeongrok Jo, Seyong Ahn, Taewhan Kim, Kyu-Myung Choi. 500-506 [doi]
- Clustering of flip-flops for useful-skew clock tree synthesisChuan Yean Tan, Rickard Ewetz, Cheng-Kok Koh. 507-512 [doi]
- Optimal die placement for interposer-based 3D ICsSergii Osmolovskyi, Johann Knechtel, Igor L. Markov, Jens Lienig. 513-520 [doi]
- Flip-chip routing with IO planning considering practical pad assignment constraintsTao-Chun Yu, Shao-Yun Fang. 521-526 [doi]
- Accelerator-centric deep learning systems for enhanced scalability, energy-efficiency, and programmabilityMinsoo Rhu. 527-533 [doi]
- Running sparse and low-precision neural network: When algorithm meets hardwareBing Li, Wei Wen, Jiachen Mao, Sicheng Li, Yiran Chen, Hai Helen Li. 534-539 [doi]
- Architectures and algorithms for user customization of CNNsBarend Harris, Mansureh S. Moghaddam, Duseok Kang, Inpyo Bae, Euiseok Kim, Hyemi Min, Hansu Cho, Sukjin Kim, Bernhard Egger, Soonhoi Ha, Kiyoung Choi. 540-547 [doi]
- Rethinking self-balancing binary search tree over phase change memory with write asymmetryChieh-Fu Chang, Che-Wei Chang, Yuan-Hao Chang, Ming-Chang Yang. 548-553 [doi]
- Energy, latency, and lifetime improvements in MLC NVM with enhanced WOM codeHuizhang Luo, Liang Shi, Qiao Li, Chun Jason Xue, Edwin Hsing-Mean Sha. 554-559 [doi]
- Scheduling multi-rate real-time applications on clustered many-core architectures with memory constraintsMatthias Becker 0004, Saad Mubeen, Dakshina Dasari, Moris Behnam, Thomas Nolte. 560-567 [doi]
- PT-spike: A precise-time-dependent single spike neuromorphic architecture with efficient supervised learningTao Liu, Lei Jiang, Yier Jin, Gang Quan, Wujie Wen. 568-573 [doi]
- Fully parallel RRAM synaptic array for implementing binary neural network with (+1, -1) weights and (+1, 0) neuronsXiaoyu Sun, Xiaochen Peng, Pai-Yu Chen, Rui Liu, Jae-sun Seo, Shimeng Yu. 574-579 [doi]
- Spintronics based stochastic computing for efficient Bayesian inference systemXiaotao Jia, Jianlei Yang, Zhaohao Wang, Yiran Chen, Hai Helen Li, Weisheng Zhao. 580-585 [doi]
- SAT-based area recovery in structural technology mappingBruno de O. Schmitt, Alan Mishchenko, Robert K. Brayton. 586-591 [doi]
- A two-step search engine for large scale boolean matching under NP3 equivalenceChak-Wa Pui, Peishan Tu, Haocheng Li, Gengjie Chen, Evangeline F. Y. Young. 592-598 [doi]
- Low-cost hardware architectures for mersenne modulo functional unitsKeith A. Campbell, Chen-Hsuan Lin, Deming Chen. 599-604 [doi]
- A low-power high-speed accuracy-controllable approximate multiplier designTongxin Yang, Tomoaki Ukezono, Toshinori Sato. 605-610 [doi]
- Exploration of approximate multipliers design space using carry propagation free compressorsSina Boroumand, Hadi Parandeh-Afshar, Philip Brisk, Siamak Mohammadi. 611-616 [doi]
- Low-power implementation of Mitchell's approximate logarithmic multiplication for convolutional neural networksMin-Soo Kim, Alberto A. Del Barrio, Román Hermida, Nader Bagherzadeh. 617-622 [doi]
- Accelerating electromigration aging for fast failure detection for nanometer ICsZeyu Sun, Sheriff Sadiqbatcha, Hengyang Zhao, Sheldon X.-D. Tan. 623-630 [doi]
- Efficient worst-case timing analysis of critical-path delay under workload-dependent aging degradationShumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato. 631-636 [doi]
- Balancing resiliency and energy efficiency of functional units in ultra-low power systemsMohammad Saber Golanbari, Anteneh Gebregiorgis, Elyas Moradi, Saman Kiamehr, Mehdi Baradaran Tahoori. 637-644 [doi]
- Mechanical strain and temperature aware design methodology for thin-film transistor based pseudo-CMOS logic arrayWenyu Sun, Yuxuan Huang, Qinghang Zhao, Fei Qiao, Tsung-Yi Ho, Xiaojun Guo, Huazhong Yang, Yongpan Liu. 645-650 [doi]
- Process design kit for flexible hybrid electronicsLeilai Shao, Tsung-Ching Huang, Ting Lei, Zhenan Bao, Raymond G. Beausoleil, Kwang-Ting Cheng. 651-657 [doi]
- From silicon to printed electronics: A coherent modeling and design flow approach based on printed electrolyte gated FETsGabriel Cadilha Marques, Farhan Rasheed, Jasmin Aghassi-Hagmann, Mehdi Baradaran Tahoori. 658-663 [doi]
- A best-fit mapping algorithm to facilitate ESOP-decomposition in Clifford+T quantum network synthesisGiulia Meuli, Mathias Soeken, Martin Roetteler, Nathan Wiebe, Giovanni De Micheli. 664-669 [doi]
- Exploiting coding techniques for logic synthesis of reversible circuitsAlwin Zulehner, Robert Wille. 670-675 [doi]
- Functional decomposition using majorityZhufei Chu, Mathias Soeken, Yinshui Xia, Giovanni De Micheli. 676-681 [doi]
- CANNA: Neural network acceleration using configurable approximation on GPGPUMohsen Imani, Max Masich, Daniel Peroni, Pushen Wang, Tajana Rosing. 682-689 [doi]
- Task assignment and scheduling in MPSoC under process variation: A stochastic approachBehnam Khodabandeloo, Ahmad Khonsari, Alireza Majidi, Mohammad Hassan Hajiesmaili. 690-695 [doi]
- DarkMem: Fine-grained power management of local memories for accelerators in embedded systemsChristian Pilato, Luca P. Carloni. 696-701 [doi]
- CryptoBlaze: A partially homomorphic processor with multiple instructions and non-deterministic encryption supportFlorencia Irena, Daniel Murphy, Sri Parameswaran. 702-708 [doi]
- PMU-Trojan: On exploiting power management side channel for information leakageMd. Nazmul Islam, Sandip Kundu. 709-714 [doi]
- A low-overhead PUF based on parallel scan designWenxuan Wang, Aijiao Cui, Gang Qu, Huawei Li. 715-720 [doi]
- Security analysis and enhancement of model compressed deep learning systems under adversarial attacksQi Liu, Tao Liu, Zihao Liu, Yanzhi Wang, Yier Jin, Wujie Wen. 721-726 [doi]
- HLIFT: A high-level information flow tracking method for detecting hardware TrojansChenguang Wang, Yici Cai, Qiang Zhou 0001. 727-732 [doi]
- System-on-chip security architecture and CAD framework for hardware patchAtul Prasad Deb Nath, Sandip Ray, Abhishek Basak, Swamp Bhunia. 733-738 [doi]