Abstract is missing.
- Concept Recognition in Production Yield Data AnalyticsMatthew Nero, Chuanhe Jay Shan, Li-C. Wang, Nik Sumikawa. 1-10 [doi]
- Analysis of Process Variations, Defects, and Design-Induced Coupling in MemristorsArjun Chaudhuri, Krishnendu Chakrabarty. 1-10 [doi]
- Test of Supply Noise for Emerging Non-Volatile MemoryMohammad Nasim Imtiaz Khan, Swaroop Ghosh. 1-10 [doi]
- Advanced Uniformed Test Approach For Automotive SoCsT. Kogan, Y. Abotbol, G. Boschi, Gurgen Harutyunyan, N. Martirosyan, Yervant Zorian. 1-10 [doi]
- Lightweight Timing Channel Protection for Shared DRAM ControllerYing Wang, Wen Li, Huawei Li, Xiaowei Li. 1-10 [doi]
- A Stressed Eye Testing Module for Production Test of 30-Gbps NRZ Signal InterfacesKiyotaka Ichiyama, Takashi Kusaka, Masahiro Ishida. 1-10 [doi]
- Fast and accurate linearity test for DACs with various architectures using segmented modelsShravan K. Chaganti, Abalhassan Sheikh, Sumit Dubey, Frank Ankapong, Nitin Agarwal, Degang Chen. 1-10 [doi]
- Fault Tolerance for RRAM-Based Matrix OperationsMengyun Liu, Lixue Xia, Yu Wang, Krishnendu Chakrabarty. 1-10 [doi]
- Deterministic Stellar BIST for In-System Automotive TestYingdi Liu, Nilanjan Mukherjee 0001, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer. 1-9 [doi]
- Optimizing the Use of Simulations for Commissioning with Systems Engineering Principles and Objective AnalysisTrevor Ault. 1-6 [doi]
- Improving Power, Performance and Area with Test: A Case StudyTeresa L. McLaurin, Ignatius P. Lawrence. 1-10 [doi]
- Hardware IP Trust Validation: Learn (the Untrustworthy), and VerifyTamzidul Hoque, Jonathan Cruz, Prabuddha Chakraborty, Swarup Bhunia. 1-10 [doi]
- On-Chip Toggle Generators to Provide Realistic Conditions during Test of Digital 2D-SoCs and 3D-SICsLeonidas Katselas, Alkis A. Hatzopoulos, Hailong Jiao, Christos Papameletis, Erik Jan Marinissen. 1-9 [doi]
- Generating Compact Test Patterns for DC and AC Faults Using One ATPG RunYi-Cheng Kung, Kuen-Jong Lee, Sudhakar M. Reddy. 1-10 [doi]
- Testing Resistive Memories: Where are We and What is Missing?Moritz Fieback, Mottaqiallah Taouil, Said Hamdioui. 1-9 [doi]
- EMFORCED: EM-based Fingerprinting Framework for Counterfeit Detection with Demonstration on Remarked and Cloned ICsAndrew Stern, Ulbert Botero, Bicky Shakya, Hao-Ting Shen, Domenic Forte, Mark Tehranipoor. 1-9 [doi]
- XLBIST: X-Tolerant Logic BISTPeter Wohl, John A. Waicukauski, Gregory A. Maston, Jonathon E. Colburn. 1-9 [doi]
- Online Scan Diagnosis : A Novel Approach to Volume DiagnosisI-De Huang, Pallav Gupta, Loganathan Lingappan, Vijay Gangaram. 1-10 [doi]
- Machine Learning for Yield Learning and OptimizationYibo Lin, Mohamed Baker Alawieh, Wei Ye, David Z. Pan. 1-10 [doi]
- Improving Diagnosis Resolution and Performance at High Compression RatiosSameer Chillarige, Atul Chhabra, Anil Malik, Bharath Nandakumar, Joe Swenton, Krishna Chakravadhanula. 1-8 [doi]
- Towards Provably Secure Logic Locking for Hardening Hardware Security Dissertation Summary: IEEE TTTC E.J. McCluskey Doctoral Thesis Award CompetitionMuhammad Yasin, Ozgur Sinanoglu. 1-10 [doi]
- Design Automation for Intelligent Automotive SystemsShuyue Lan, Chao Huang, Zhilu Wang, Hengyi Liang, Wenhao Su, Qi Zhu 0002. 1-10 [doi]
- Detection of Low Power Trojans in Standard Cell Designs using Built-in Current SensorsBasim Shanyour, Spyros Tragoudas. 1-10 [doi]
- Access-Time Minimization in the IEEE 1687 Network Using Broadcast and Hardware ParallelismZhanwei Zhong, Guoliang Li, Qinfu Yang, Krishnendu Chakrabarty. 1-10 [doi]
- Fine-Grained Adaptive Testing Based on Quality PredictionMengyun Liu, Renjian Pan, Fangming Ye, Xin Li, Krishnendu Chakrabarty, Xinli Gu. 1-10 [doi]
- DPPM Reduction Methods and New Defect Oriented Test Methods Applied to Advanced FinFET TechnologiesW. Howell, Friedrich Hapke, E. Brazil, S. Venkataraman, R. Datta, Andreas Glowatz, Wilfried Redemund, J. Schmerberg, Anja Fast, Janusz Rajski. 1-10 [doi]
- A PVT-Resilient No-Touch DFT Methodology for Prebond TSV TestingSourav Das, Fei Su, Sreejit Chakravarty. 1-10 [doi]
- On the use of Bayesian Networks for Resource-Efficient Self-Calibration of Analog/RF ICsMartin Andraud, Laura Isabel Galindez Olascoaga, Yichuan Lu, Yiorgos Makris, Marian Verhelst. 1-10 [doi]
- Hardware Dithering: A Run-Time Method for Trojan Neutralization in Wireless Cryptographic ICsChristiana Kapatsori, Yu Liu, Angelos Antonopoulos, Yiorgos Makris. 1-7 [doi]
- Test methodology for PCHB/PCFB Asynchronous CircuitsTing-Yu Shen, Chia-Cheng Pai, Tsai-Chieh Chen, James Chien-Mo Li, Samuel Pan. 1-8 [doi]
- Electrical Modeling of STT-MRAM DefectsLizhou Wu, Mottaqiallah Taouil, Siddharth Rao, Erik Jan Marinissen, Said Hamdioui. 1-10 [doi]
- Built-In Self-Diagnosis and Fault-Tolerant Daisy-Chain Design in MEDA BiochipsLing Zhang, Zipeng Li, Krishnendu Chakrabarty. 1-10 [doi]
- Scalable Hardware Trojan Activation by Interleaving Concrete Simulation and Symbolic ExecutionAlif Ahmed, Farimah Farahmandi, Yousef Iskander, Prabhat Mishra. 1-10 [doi]
- Improving Analog Functional Safety Using Data-Driven Anomaly DetectionFei Su, Prashant Goteti. 1-10 [doi]
- An Effective Methodology for Automated Diagnosis of Functional Pattern Failures to Support Silicon DebugPallav Gupta. 1-8 [doi]
- On New Class of Test Points and Their ApplicationsJanusz Rajski, Jerzy Tyszer, Justyna Zawada. 1-9 [doi]
- Defect injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAMSarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori, G. Tshagharyan, H. Grigoryan, Gurgen Harutyunyan, Yervant Zorian. 1-10 [doi]
- Total Critical Area Based TestingFriedrich Hapke, Peter C. Maxwell. 1-10 [doi]
- Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon ValidationFrancisco E. Rangel-Patino, José Ernesto Rayas-Sánchez, Nagib Hakim. 1-10 [doi]
- On Close-to-Functional Test SequencesIrith Pomeranz. 1-8 [doi]
- Hypercompression of Test PatternsYu Huang 0005, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer, Chen Wang 0014. 1-9 [doi]
- Self-Learning Health-Status Analysis for a Core Router SystemShi Jin, Zhaobo Zhang, Krishnendu Chakrabarty, Xinli Gu. 1-10 [doi]
- An Autonomous System View To Apply Machine LearningLi-C. Wang. 1-10 [doi]
- Production Tests Coverage Analysis in the Simulation EnvironmentNiveditha Manjunath, Dieter Haerle, Stephen Sabanal, Herbert Eichinger, Hermann Tauber, Andreas Machne, Christian Manthey, Mikko Vaananen, Radu Grosu, Dejan Nickovic. 1-7 [doi]
- Case Study and Advanced Functional Safety Solution for Automotive SoCsM. Casarsa, Gurgen Harutyunyan. 1-8 [doi]
- IJTAG Integrity Checking with Chained HashingSenwen Kan, Jennifer Dworak. 1-10 [doi]
- Modeling and Testing of Aging Faults in FinFET Memories for Automotive ApplicationsG. Tshagharyan, Gurgen Harutyunyan, Yervant Zorian, Anteneh Gebregiorgis, Mohammad Saber Golanbari, Rajendra Bishnoi, Mehdi Baradaran Tahoori. 1-10 [doi]
- Improving Diagnosis Efficiency via Machine LearningQicheng Huang, Chenlei Fang, Soumya Mittal, R. D. Shawn Blanton. 1-10 [doi]
- Pre-silicon Formal Verification of JTAG Instruction Opcodes for SecurityNicole Fern, Kwang-Ting (Tim) Cheng. 1-9 [doi]
- Safe AI for CPS (Invited Paper)Nathan Fulton, André Platzer. 1-7 [doi]
- Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated CircuitsErik Jan Marinissen, Ferenc Fodor, Arnita Podpod, Michele Stucchi, Yu-Rong Jian, Cheng-Wen Wu. 1-10 [doi]
- TimingSAT: Decamouflaging Timing-based Logic ObfuscationMeng Li 0004, Kaveh Shamsi, Yier Jin, David Z. Pan. 1-10 [doi]
- Variation-Aware Hardware Trojan Detection through Power Side-channelFakir Sharif Hossain, Michihiro Shintani, Michiko Inoue, Alex Orailoglu. 1-10 [doi]
- Advanced ECC-Based FIT Rate Mitigation Technique for Automotive SoCsH. Grigoryan, Samvel K. Shoukourian, Gurgen Harutyunyan, Yervant Zorian, Costas Argyrides. 1-6 [doi]
- Artificial Neural Network Based Test Escape Screening Using Generative ModelMichihiro Shintani, Michiko Inoue, Yoshiyuki Nakamura. 1-8 [doi]
- An Effective Intra-Cell Diagnosis Flow for Industrial SRAMsT.-P. Ho, E. Faehn, Arnaud Virazel, Alberto Bosio, P. Girard. 1-8 [doi]
- Influence-Directed Explanations for Deep Convolutional NetworksKlas Leino, Shayak Sen, Anupam Datta, Matt Fredrikson, Linyi Li. 1-8 [doi]
- Polynomial Chaos modeling for jitter estimation in high-speed linksMajid Ahadi Dolatsara, Huan Yu, Jose Ale Hejase, Wiren Dale Becker, Madhavan Swaminathan. 1-10 [doi]
- A New Technique to Generate Test Sequences for Reconfigurable Scan NetworksRiccardo Cantoro, Aleksa Damljanovic, Matteo Sonza Reorda, Giovanni Squillero. 1-9 [doi]