Amit Agarwal 0001 - researchr alias

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Viewing Publication 1 - 25 from 25

2023

A 7-Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOSRaghavan Kumar, Vikram B. Suresh, Sachin Taneja, Mark A. Anders 0001, Steven Hsu, Amit Agarwal 0001, Vivek De, Sanu K. Mathew. jssc, 58(4):1106-1116, 2023. [doi]

2022

On-Chip High-Resolution Timing Characterization Circuits for Memory IPsAmit Agarwal 0001, Steven Hsu, Mark A. Anders 0001, Gunjan Pandya, Ram Krishnamurthy 0001, James W. Tschanz, Vivek De. esscirc 2022: 377-380 [doi]

2.4GHz, Double-Buffered, 4kb Standard-Cell-Based Register File with Low-Power Mixed-Frequency Clocking for Machine Learning AcceleratorsSteven Hsu, Amit Agarwal 0001, Mark A. Anders 0001, Arnab Raha, Raymond Sung, Deepak Mathaikutty, Ram Krishnamurthy 0001, James W. Tschanz, Vivek De. vlsit 2022: 22-23 [doi]

A 7Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOSRaghavan Kumar, Vikram B. Suresh, Sachin Taneja, Mark A. Anders 0001, Steven Hsu, Amit Agarwal 0001, Vivek De, Sanu Mathew. vlsit 2022: 138-139 [doi]

An 8.3-to-18Gbps Reconfigurable SCA-Resistant/Dual-Core/Blind-Bulk AES Engine in Intel 4 CMOSRaghavan Kumar, Vikram B. Suresh, Mark A. Anders 0001, Steven K. Hsu, Amit Agarwal 0001, Vivek K. De, Sanu K. Mathew. isscc 2022: 1-3 [doi]

2021

2020

25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOSAmit Agarwal 0001, Steven Hsu, Simeon Realov, Mark Anders, Gregory K. Chen, Monodeep Kar, Raghavan Kumar, Huseyin Sumbul, Phil C. Knag, Himanshu Kaul, Sanu Mathew, Mahesh Kumashikar, Ram Krishnamurthy, Vivek De. isscc 2020: 392-394 [doi]

25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating RangeMark A. Anders, Himanshu Kaul, Seongjong Kim, Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Phil C. Knag, Monodeep Kar, Steven K. Hsu, Amit Agarwal 0001, Vikram B. Suresh, Sanu K. Mathew, Ram K. Krishnamurthy, Vivek De. isscc 2020: 396-398 [doi]

Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOSSteven Hsu, Amit Agarwal 0001, Simeon Realov, Mark Anders, Gregory K. Chen, Monodeep Kar, Raghavan Kumar, Huseyin Sumbul, Phil V. Knag, Himanshu Kaul, Vikram B. Suresh, Sanu Mathew, Iqbal Rajwani, Satish Damaraju, Ram Krishnamurthy, Vivek De. vlsic 2020: 1-2 [doi]

A Ray-Casting Accelerator in 10nm CMOS for Efficient 3D Scene Reconstruction in Edge Robotics and Augmented Reality ApplicationsMonodeep Kar, Amit Agarwal 0001, Steven Hsu, David Moloney, Gregory K. Chen, Raghavan Kumar, Huseyin Sumbul, Phil V. Knag, Mark Anders, Himanshu Kaul, Jonathan Byrne, Luca Sarti, Ram Krishnamurthy, Vivek De. vlsic 2020: 1-2 [doi]

A 617 TOPS/W All Digital Binary Neural Network Accelerator in 10nm FinFET CMOSPhil C. Knag, Gregory K. Chen, Huseyin Ekin Sumbul, Raghavan Kumar, Mark A. Anders, Himanshu Kaul, Steven K. Hsu, Amit Agarwal 0001, Monodeep Kar, Seongjong Kim, Ram K. Krishnamurthy. vlsic 2020: 1-2 [doi]

2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key AdditionRaghavan Kumar, Vikram B. Suresh, Monodeep Kar, Sudhir Satpathy, Mark A. Anders, Himanshu Kaul, Amit Agarwal 0001, Steven Hsu, Gregory K. Chen, Ram K. Krishnamurthy, Vivek De, Sanu K. Mathew. jssc, 55(4):945-955, 2020. [doi]

2019

A 54% Power-Saving Static Fully-Interruptible Single-Phase-Clocked Shared-Keeper Flip-Flop in 14nm CMOSAmit Agarwal 0001, Steven Hsu, Monodeep Kar, Mark Anders, Himanshu Kaul, Raghavan Kumar, Vikram B. Suresh, Sanu Mathew, Ram Krishnamurthy, Vivek De. asscc 2019: 137-140 [doi]

A Microwatt-Class Always-On Sensor Fusion Engine Featuring Ultra-Low-Power AOI Clocked Circuits in 14nm CMOSSteven Hsu, Amit Agarwal 0001, Monodeep Kar, Mark Anders, Himanshu Kaul, Raghavan Kumar, Sudhir Satpathy, Vikram Suresh, Sanu Mathew, Ram Krishnamurthy, Vivek De. vlsic 2019: 50 [doi]

A 220-900mV 179Mcode/s 36pJ/code Canonical Huffman Encoder for DEFLATE Compression in 14nm CMOSSudhir Satpathy, Vikram Suresh, Raghavan Kumar, Vinodh Gopal, James Guilford, Kirk Yap, Mark Anders, Himanshu Kaul, Amit Agarwal 0001, Steven Hsu, Ram Krishnamurthy, Sanu Mathew. cicc 2019: 1-4 [doi]

A 225-950mV 1.5Tbps/W Whirlpool Hashing Accelerator for Secure Automotive Platforms in 14nm CMOSVikram Suresh, Sudhir Satpathy, Raghavan Kumar, Mark Anders, Himanshu Kaul, Amit Agarwal 0001, Steven Hsu, Ram Krishnamurthy, Sanu Mathew. cicc 2019: 1-4 [doi]

A 250Mv, 0.063J/Ghash Bitcoin Mining Engine in 14nm CMOS Featuring Dual-Vcc Sha256 Datapath and 3-Phase Latch Based ClockingVikram Suresh, Sudhir Satpathy, Raghavan Kumar, Mark Anders, Himanshu Kaul, Amit Agarwal 0001, Steven Hsu, Ram Krishnamurthy, Vivek De, Sanu Mathew. vlsic 2019: 32 [doi]

2014

2010

2007

A 200mV to 1.2V, 4.4MHz to 6.3GHz, 48×42b 1R/1W programmable register file in 65nm CMOSAmit Agarwal 0001, Nilanjan Banerjee, Steven K. Hsu, Ram K. Krishnamurthy, Kaushik Roy 0001. esscirc 2007: 316-319 [doi]

2005

Process variation in embedded memories: failure analysis and variation aware architectureAmit Agarwal 0001, Bipul C. Paul, Saibal Mukhopadhyay, Kaushik Roy 0001. jssc, 40(9):1804-1814, 2005. [doi]

2003

t low-leakage gated-ground cache for deep submicronAmit Agarwal 0001, Hai Li, Kaushik Roy 0001. jssc, 38(2):319-328, 2003. [doi]

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