Table of Contents

• What are the driving forces of DRAM?Yiming Zhu. 1-4 [doi]
• Memory Centric Computing, The Foundation of the Next Smart SocietyKyo Won Jin. 5-8 [doi]
• A 45nm 76-81GHz CMOS Radar Receiver for Automotive ApplicationsDebapriya Sahu, Rittu Sachdev-Singh, Harikrishna Parthasarathy, Rohit Chatterjee, Brian P. Ginsburg, Daniel Breen, Karan Bhatia, Sudhir Polarouthu, Vimal Edayath, Bhupendra Sharma, Meghna Agarwal, Karthik Subburaj, Anjan Prasad, Shankar Ram, Cathy Chi, Ross Kulak, Vijay Rentala, Neeraj P. Nayak. 9-12 [doi]
• An Untrimmed PVT-Robust 12-bit 1-MS/s SAR ADC IP in 55nm Deeply Depleted Channel CMOS ProcessY. Zha, Loïc Zahnd, Jiang Deng, David Ruffieux, Komail M. H. Badami, T. Mavrogordatos, Y. Matsuo, Stéphane Emery. 13-16 [doi]
• A Cost Effective Test Screening Circuit for embedded SRAM with Resume Standby on 110-nm SoC/MCUYoshisato Yokoyama, Kenji Goto, Tomohiro Miura, Yukari Ouchi, Daisuke Nakamura, Jiro Ishikawa, Shunya Nagata, Yoshiki Tsujihashi, Yuichiro Ishii. 17-20 [doi]
• A 2.666GT/s 128GB/s 14nm Memory I/O with Jitter and Crosstalk CancellationHarry Muljono, Kathy Peng, Linda Sun, Isaac Abraham, Charlie Lin, Yanjie Zhu, Chunrong Song. 21-24 [doi]
• A Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip DevicesTakuji Miki, Makoto Nagata, Hiroki Sonoda, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi. 25-28 [doi]
• A 28nm 512Kb adjacent 2T2R RRAM PUF with interleaved cell mirroring and self-adaptive splitting for extremely low bit error rate of cryptographic keyXiaoyong Xue, Jianguo Yang, Yuejun Zhang, Mingyu Wang, Hangbing Lv, Xiaoyang Zeng, Ming Liu. 29-32 [doi]
• A 0.5V Real-Time Computational CMOS Image Sensor with Programmable Kernel for Always-On Feature ExtractionTzu-Hsiang Hsu, Yen-Kai Chen, Tai-Hsing Wen, Wei-Chen Wei, Yi Ren Chen, Fu-Chun Chang, Hyunjoon Kim, Qian Chen, Bongjin Kim, Ren-Shuo Liu, Chung-Chuan Lo, Kea-Tiong Tang, Meng-Fan Chang, Chih-Cheng Hsieh. 33-34 [doi]
• A 16K SRAM-Based Mixed-Signal In-Memory Computing Macro Featuring Voltage-Mode Accumulator and Row-by-Row ADCHyunjoon Kim, Qian Chen, Bongjin Kim. 35-36 [doi]
• A 69.3% Efficiency, 6.78-MHz Wireless Power Delivery System with 0X/1X Regulating Rectifier and Reconfigurable Power AmplifierJonathan Fuh, Fu-Bin Yang, Po-Hung Chen. 37-38 [doi]
• An 80mA Capacitor-Less LDO with 6.5µA Quiescent Current and No Frequency Compensation Using Adaptive-Deadzone Ring AmplifierBohui Xiao, Praveen Kumar Venkatachala, Yang Xu, Ahmed ElShater, Calvin Yoji Lee, Spencer Leuenberger, Qadeer Ahmad Khan, Un-Ku Moon. 39-42 [doi]
• A DCM ZVS Class-D Power Amplifier for Wireless Power Transfer ApplicationsXinyuan Ge, Lin Cheng 0001, Wing-Hung Ki. 43-44 [doi]
• Time-Based Digital LDO Regualtor with Fractionally Controlled Power Transistor Strength and Fast Transient ResponseJin-Gyu Kang, Min-Gyu Jeong, Jeongpyo Park, Changsik Yoo. 45-48 [doi]
• A Single-Inductor Triple-Output Converter with an Automatic Detection of DC or AC Energy Harvesting Source for Supplying 93% Efficiency and 0.05mV/mA Cross Regulation to Wearable ElectronicsT. Nagateja, Shao-Qi Chen, Li-Cheng Chu, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai. 49-52 [doi]
• 2 8.54mW FocusNet Display LSI for Power Reduction on OLED Smart-phonesTsu-Ming Liu, Chang-Hung Tsai, Shawn Shih, Chih-Kai Chang, Jia-Ying Lin, Wayne Hsieh, Yung-Chang Chang, Chi-Cheng Ju. 53-56 [doi]
• A 47.4µJ/epoch Trainable Deep Convolutional Neural Network Accelerator for In-Situ Personalization on Smart DevicesSeungkyu Choi, Jaehyeong Sim, Myeonggu Kang, YeongJae Choi, Hyeonuk Kim, Lee-Sup Kim. 57-60 [doi]
• A Sparse-Adaptive CNN Processor with Area/Performance balanced N-Way Set-Associate PE Arrays Assisted by a Collision-Aware SchedulerZhe Yuan, Jingyu Wang, Yixiong Yang, Jinshan Yue, Zhibo Wang, Xiaoyu Feng, Yanzhi Wang, Xueqing Li, Huazhong Yang, Yongpan Liu. 61-64 [doi]
• A 2.25 TOPS/W Fully-Integrated Deep CNN Learning Processor with On-Chip TrainingCheng-Hsun Lu, Yi-Chung Wu, Chia-Hsiang Yang. 65-68 [doi]
• A Ka-Band CMOS Phase-Inverting Amplifier with 0.6 dB Gain Error and 2.5° Phase ErrorChenyu Xu, Dixian Zhao. 69-72 [doi]
• A High-Performance Low Complexity All-Digital Fractional Clock MultiplierNahla T. Abou-El-Kheir, Ralph D. Mason, Mingze Li, Mustapha C. E. Yagoub. 73-76 [doi]
• A DC-43.5 GHz CMOS Switched-Type Attenuator with Capacitive Compensation TechniquePeng Gu, Dixian Zhao. 77-78 [doi]
• A 28-GHz Compact SPDT Switch Using LC-Based Spiral Transmission Lines in 65-nm CMOSXiangyu Meng, Zhenpeng Zheng, Jiaqi Zhang, C. Patrick Yue. 79-80 [doi]
• A 20-GHz Ultra-Low-Power LNA Using gm-Boosted and Current-Reuse Techniques in 65-nm CMOS for Satellite Communication TerminalsJiajun Zhang, Dixian Zhao. 81-82 [doi]
• A 4-GHz Sub-harmonically Injection-Locked Phase-Locked Loop with Self-Calibrated Injection Timing and PulsewidthXuefan Jin, Dong-Seok Kang, Youngjun Ko, Kee-Won Kwon, Jung-Hoon Chun. 83-86 [doi]
• A 9.4MHz-to-2.4GHz Jitter-Power Reconfigurable Fractional-N Ring PLL for Multi-Standard Applications in 7nm FinFET CMOS TechnologySangdon Jung, Jaehong Jung, Byungki Han, Seunghyun Oh, Jongwoo Lee. 87-90 [doi]
• A 2.4-GHz 500-µW 370-fsrms Integrated Jitter Sub-Sampling Sub-Harmonically Injection-Locked PLL in 90-nm CMOSChun-Yu Lin, Yu-Ting Hung, Tsung-Hsien Lin. 91-94 [doi]
• A Sub-Sampling PLL with Robust Operation under Supply Interference and Short Re-Locking TimeYuan Cheng Qian, Yen-Yu Chao, Shen-Iuan Liu. 95-98 [doi]
• AI and IoT for Social Value CreationYasunori Mochizuki. 99-102 [doi]
• Millimeter-Wave System-on-Chip Applications from Space Explorations to Contactless ConnectivityMau-Chung Frank Chang. 103-106 [doi]
• An Energy-Efficient BJT-Based Temperature-to-Digital Converter with ±0.13°C (3σ) Inaccuracy from -40 to 125°CRushil K. Kumar, Hui Jiang, Kofi A. A. Makinwa. 107-108 [doi]
• 2 Compact Highly-Digital Closed-Loop Single-VCO-based 1-1 SMASH Resistance-to-Digital Converter in 180nm CMOSElisa Sacco, Johan Vergauwen, Georges G. E. Gielen. 109-112 [doi]
• A Low-Noise Sub-Bandgap Reference with a ±0.64% Untrimmed Precision in 16nm FinFETMatthias Eberlein, Harald Pretl. 113-116 [doi]
• A 1.2V 86dB SNDR 500kHz BW Linear-Exponential Multi-Bit Incremental ADC Using Positive Feedback in 65nm CMOSBiao Wang, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins. 117-120 [doi]
• 2/sqrt(MHz) Noise FloorPengfei Zhai, Xiong Zhou, Yan Cai, Zheng Zhu, Fan Zhang, Zixiao Lin, Qiang Li. 121-122 [doi]
• A 265μW Continuous-Time 1-2 MASH ADC Achieving 100.6 dB SNDR in a 24 kHz BandwidthSujith Billa, Suhas Dixit, Shanthi Pavan. 123-124 [doi]
• Drop-In Energy-Performance Range Extension in Microcontrollers Beyond VDD ScalingSaurabh Jain, Longyang Lin, Massimo Alioto. 125-128 [doi]
• A 28nm fully digital voltage monitor with 16.5uV/°C accuracy and 0.8mV quantized error from -40 to 160°C for ISO26262 ASIL-D capable MCUToshifumi Uemura, Yuko Kitaji, Kazuki Fukuoka. 129-132 [doi]
• HyCUBE: A 0.9V 26.4 MOPS/mW, 290 pJ/op, Power Efficient Accelerator for IoT ApplicationsBo Wang, Manupa Karunarathne, Aditi Kulkarni Mohite, Tulika Mitra, Li-Shiuan Peh. 133-136 [doi]
• A 54% Power-Saving Static Fully-Interruptible Single-Phase-Clocked Shared-Keeper Flip-Flop in 14nm CMOSAmit Agarwal 0001, Steven Hsu, Monodeep Kar, Mark Anders, Himanshu Kaul, Raghavan Kumar, Vikram B. Suresh, Sanu Mathew, Ram Krishnamurthy, Vivek De. 137-140 [doi]
• 0.54 pJ/bit, 15Mb/s True Random Number Generator Using Probabilistic Delay Cell for Edge Computing ApplicationsFei Li, Ming Ming Wong, Aarthy Mani, Vishnu Paramasivam, Anh-Tuan Do. 141-144 [doi]
• A Smart Hardware Security Engine Combining Entropy Sources of ECG, HRV and SRAM PUF for Authentication and Secret Key GenerationSai Kiran Cherupally, Shihui Yin, Deepak Kadetotad, ChiSung Bae, Sang Joon Kim, Jae-sun Seo. 145-148 [doi]
• A Packaged Fully Digital 390GHz Harmonic Outphasing Transmitter in 28nm CMOSAlexander Standaert, Patrick Reynaert. 149-152 [doi]
• A Fully Integrated 27.5-30.5 GHz 8-Element Phased-Array Transmit Front-end Module in 65 nm CMOSAn'an Li, Yingtao Ding, Zipeng Chen, Wei Wang, Sijia Jiang, Shiyan Sun, Zhiming Chen, Baoyong Chi. 153-156 [doi]
• A 2Mbps sub-100µW Crystal-less RF Transmitter with Energy Harvesting for Multi-Channel Neural Signal AcquisitionHeng Huang, Milin Zhang, Guolin Li, Zhihua Wang. 157-160 [doi]
• Direct-Conversion Receiver Front-End for 180 GHz with 80 GHz Bandwidth in 130nm SiGePaul Stärke, Andres Seidel, Corrado Carta, Frank Ellinger. 161-164 [doi]
• A Blocker-Tolerant Direct Sampling Receiver for Wireless Multi-Channel Communication in 14nm FinFET CMOSBarosaim Sung, Chilun Lo, Jaehoon Lee, Sangdon Jung, Seungjin Kim, Jaehong Jung, Seungyong Bae, Youngsea Cho, Yong Lim, Dooseok Choi, Myeongcheol Shin, Soonwoo Choi, Byungki Han, Seunghyun Oh, Jongwoo Lee. 165-168 [doi]
• 2 Receiver Front-End for Bluetooth Low Energy (BLE) in 22 nm FD-SOI with Zero External ComponentsEhsan Kargaran, Carl Bryant, Danilo Manstretta, Jon Strange, Rinaldo Castello. 169-172 [doi]
• A 4-Mbps 41-pJ/bit On-off Keying Transceiver for Body-channel Communication with Enhanced Auto Loss Compensation TechniqueJian Zhao 0004, Jingna Mao, Wenyu Sun, Yuxuan Huang, Yixiong Yang, Huazhong Yang, Yongpan Liu. 173-176 [doi]
• A battery-less 31 µW HBC receiver with RF energy harvester for implantable devicesJihee Lee, Jaeeun Jang, Jaehyuk Lee, Hoi-Jun Yoo. 177-180 [doi]
• A Piezoelectric Energy Harvesting Interface for Irregular High Voltage Input with Partial Electric Charge Extraction with 3.9× Extraction ImprovementMuhammad Bilawal Khan, Hassan Saif, Yoonmyung Lee. 181-184 [doi]
• A 100-pA Adaptive-FOCV MPPT Circuit with >99.6% Tracking Efficiency for Indoor Light Energy HarvestingPeng-Chang Huang, Tai-Haur Kuo. 185-188 [doi]
• A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping CapabilityMin-Jae Seo, Dong-Hwan Jin, Ye-Dam Kim, Jong Pal Kim, Dong-Jin Chang, Won-Mook Lim, Jae-Hyun Chung, Chang-Un Park, Eun-Ji An, Seung-Tak Ryu. 189-192 [doi]
• A 68 dB SNDR Compiled Noise-Shaping SAR ADC With On-Chip CDAC CalibrationHarald Garvik, Carsten Wulff, Trond Ytterdal. 193-194 [doi]
• nd-order Noise-Shaping SAR ADC in 65nm CMOSJae Sik Yoon, Jiyoon Hong, Jintae Kim. 195-196 [doi]
• nd-Order $\Delta\Sigma$ ADCAkshay Jayaraj, Abhijit Das, Srinivas Arcot, Arindam Sanyal. 197-200 [doi]
• A 110.3-bits/min 8-Ch SSVEP-based Brain-Computer Interface SoC with 87.9% AccuracyWooseok Byun, Dokyun Kim, Sung-Yeon Kim, Ji-Hoon Kim. 201-204 [doi]
• FPGA-Based Sparsity-Aware CNN Accelerator for Noise-Resilient Edge-Level Image RecognitionSeungsik Moon, Hyunhoon Lee, Younghoon Byun, Jongmin Park, Junseo Joe, Seokha Hwang, Sunggu Lee, Youngjoo Lee. 205-208 [doi]
• Flexible Low Power CNN Accelerator for Edge Computing with Weight TuningMiaorong Wang, Anantha P. Chandrakasan. 209-212 [doi]
• An Asynchronous Reconfigurable SNN Accelerator With Event-Driven Time Step UpdateJilin Zhang, Hui Wu, Jinsong Wei, Shaojun Wei, Hong Chen. 213-216 [doi]
• A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge ProcessorsZhixiao Zhang, Jia-Jing Chen, Xin Si, Yung-Ning Tu, Jian-Wei Su, Wei-Hsing Huang, Jing-Hong Wang, Wei-Chen Wei, Yen-Cheng Chiu, Je-Min Hong, Shyh-Shyuan Sheu, Sih-Han Li, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang. 217-218 [doi]
• A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP ApplicationsJonathan Narinx, Robert Giterman, Andrea Bonetti, Nicolas Frigerio, Cosimo Aprile, Andreas Burg, Yusuf Leblebici. 219-222 [doi]
• Configurable BCAM/TCAM Based on 6T SRAM Bit Cell and Enhanced Match Line ClampingJongeun Koo, Eunhwan Kim, Seunghyun Yoo, Taesu Kim, Sungju Ryu, Jae-Joon Kim. 223-226 [doi]
• Sub-ns Access Sub-mW/GHz 32 Kb SRAM with 0.45 V Cross-Point-5T Cell and Built-in Y_ LineC. Y. He, K. H. Tang, T. S. Chen, K. Y. Chang, C. H. Lin, K. Sato, S. J. Jou, P. H. Chen, H. M. Chen, B. D. Rong, K. Itoh. 227-230 [doi]
• Privacy-Aware Data-Lifetime Control NAND Flash System for Right to be Forgotten with In-3D Vertical Cell ProcessingShun Suzuki, Kyoji Mizoguchi, Hikaru Watanabe, Toshiki Nakamura, Yoshiaki Deguchi, Keita Mizushina, Ken Takeuchi. 231-234 [doi]
• A 1.64mW Differential Super Source-Follower Buffer with 9.7GHz BW and 43dB PSRR for Time-Interleaved ADC Applications in 10nmYizhak Shifman, Yoel Krupnik, Udi Virobnik, Ahmad Khairi, Yosi Sanhedrai, Ariel Cohen 0001. 235-238 [doi]
• A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFETGain Kim, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Hazar Yueksel, Cosimo Aprile, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Hyeon-Min Bae, Andreas Burg, Thomas Toifl, Yusuf Leblebici. 239-240 [doi]
• A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Low-Power Multiphase Clock GeneratorZhao Zhang, Guang Zhu, Can Wang, Li Wang, C. Patrick Yue. 241-242 [doi]
• A Maximum-Eye-Tracking CDR with Biased Data-Level and Eye Slope Detector for Optimal Timing AdaptationHye-Yoon Joo, Deog Kyoon Jeong. 243-244 [doi]
• A 200-MHz Wide Input Range CMOS Passive Rectifier with Active Bias TunningXiaofei Li, Fangyu Mao, Pyungwoo Yeon, Yan Lu 0002, Maysam Ghovanloo, Rui P. Martins. 245-246 [doi]
• A 7.5 - 42V Input High-VCR Monolithic DC-DC Converter Using Stacked Isolated SC CoresElly De Pelecijn, Michiel Steyaert. 247-250 [doi]
• A 918MHz Wide-Range CMOS Rectifier with Diode-Feeding and Switch-Capacitor-Based Load Modulation TechniqueChen-Yi Kuo, Chun-An Lu, Yu-Te Liao. 251-254 [doi]
• A CMOS Switched-Capacitor Boost Mode Envelope Tracking Regulator with 4% Efficiency Improvement at 7.7dB PAPR for 20MHz LTE Envelope Tracking RF Power AmplifiersNeha Kumari, Shang-Hsien Yang, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai. 255-258 [doi]
• A Conversion-Ratio-Insensitive High Efficiency Soft-Charging-Based SC DC-DC Boost Converter for Energy Harvesting in Miniature Sensor SystemsJunyoung Park, Hyungmin Gi, Seungchul Jung, Sang Joon Kim, Yoonmyung Lee. 259-262 [doi]
• 33us, 94uJ Optimal Ate Pairing Engine on BN Curve over 254b Prime Field in 65nm CMOS FDSOIMakoto Ikeda, Tadayuki Ichihashi, Hiromitsu Awano. 263-266 [doi]
• An IoT Sensor Node SoC with Dynamic Power Scheduling for Sustainable Operation in Energy Harvesting EnvironmentYuji Yano, Seiya Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, Tetsuya Hirose, Masaya Miyahara, Teruki Someya, Kenichi Okada, Ippei Akita, Yoshihiko Kurui, Hideyuki Tomizawa, Masahiko Yoshimoto. 267-270 [doi]
• 2 65.38Gb/s Stochastic LDPC Decoder for IEEE 802.3an in 65 nmQichen Zhang, Yun Chen, Xiaoyang Zeng, Keshab K. Parhi, Borivoje Nikolic. 271-274 [doi]
• A Millimeter Wave Digital CMOS Baseband Transceiver for Wireless LAN ApplicationsKang-Lun Chiu, Hsun-Wei Chan, Wei-Che Lee, Chang-Ting Wu, Henry Lopez Davila, Hung-Chih Liu, Meng Yuan Huang, Chun-Yi Liu, Tsai-Hua Lee, Hsin-Ting Chang, Chih-Wei Jen, Nien-Hsiang Chang, Pei-Yun Tsai, Yen-Cheng Kuan, Shyh-Jye Jou. 275-278 [doi]
• A 23-mW 60-GHz Differential Sub-Sampling PLL with an NMOS-Only Differential-Inductively-Tuned VCOBingwei Jiang, Howard C. Luong. 279-282 [doi]
• 2 440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOSZunsong Yang, Yong Chen 0005, Pui-In Mak, Rui P. Martins. 283-284 [doi]
• A 360-456 MHz PLL frequency synthesizer with digitally controlled charge pump leakage calibrationPeilin Yang, Yanshu Guo, Hanjun Jiang, Zhihua Wang. 285-286 [doi]
• A 12-GHz All-Digital Calibration-Free FMCW Signal Generator Based on a Retiming Fractional Frequency DividerZhengkun Shen, Heyi Li, Haoyun Jiang, Zherui Zhang, Junhua Liu, Huailin Liao. 287-290 [doi]
• A 100Mb/s 3.5GHz Fully-Balanced BFOOK Modulator Based on Integer-N Hyrbrid PLLCong Ding 0004, Haixin Song, Woogeun Rhee, Zhihua Wang. 291-294 [doi]
• 2/Ch. 0.43% Gain Mismatch Orthogonal Code Chopping Instrumentation Amplifier SoC for Bio-Signal AcquisitionJeong Hoan Park, Tao Tang, Lian Zhang, Kian Ann Ng, Jerald Yoo. 295-296 [doi]
• A 10 $\mu \mathrm{W}-74.6\mathrm{dB}$ THD Arterial Pulse Waveform Sensing System with Automatic Bridge-Offset Calibration and Super Class-AB Output StageYu-Pin Hsu, Zemin Liu, Mona Mostafa Hella. 297-300 [doi]
• A 0.012 mm2, $1.5 \mathrm{G}\Omega$ ZIN Intrinsic Feedback Capacitor Instrumentation Amplifier for Bio-Potential Recording and Respiratory MonitoringLian Zhang, Tao Tang, Jeong Hoan Park, Jerald Yoo. 301-304 [doi]
• T/R-Switch Composed of 3 High-Voltage MOSFETs with 12.1 µW Consumption that can Perform Per-channel TX to RX Self-Loopback AC Tests for 3D Ultrasound Imaging with 3072-channel TransceiverShinya Kajiyama, Yutaka Igarashi, Toru Yazaki, Yusaku Katsube, Takuma Nishimoto, Tatsuo Nakagawa, Yohei Nakamura, Yoshihiro Hayashi, Taizo Yamawaki. 305-308 [doi]
• A High DR High-Input-Impedance Programmable-Gain ECG Acquisition Interface with Non-inverting Continuous Time Sigma-Delta ModulatorJunhao Liang, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins, Hanjun Jiang. 309-312 [doi]