Sub-ns Access Sub-mW/GHz 32 Kb SRAM with 0.45 V Cross-Point-5T Cell and Built-in Y_ Line

C. Y. He, K. H. Tang, T. S. Chen, K. Y. Chang, C. H. Lin, K. Sato, S. J. Jou, P. H. Chen, H. M. Chen, B. D. Rong, K. Itoh. Sub-ns Access Sub-mW/GHz 32 Kb SRAM with 0.45 V Cross-Point-5T Cell and Built-in Y_ Line. In IEEE Asian Solid-State Circuits Conference, A-SSCC 2019, Macau, SAR, China, November 4-6, 2019. pages 227-230, IEEE, 2019. [doi]

Abstract

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