Table of Contents

• The Future of Short Reach InterconnectDavide Tonietto. 1-8 [doi]
• Semiconductors take the driver's seat - challenges and opportunities for the car of the futureTim Gutheit. 9-11 [doi]
• Integrated Circuits as Key Enabler for today's Smart MEMS SensorsDirk Droste, Horst Symanzik, Timo Gießelmann, Markus Ulm, Ivano Galdi, Riccardo Campagna. 12-16 [doi]
• The Next "Automation Age": How Semiconductor Technologies Are Changing Industrial Systems and ApplicationsDomenico Arrigo, Claudio Adragna, Vincenzo Marano, Rachela Pozzi, Fulvio Pulicelli, Francesco Pulvirenti. 17-24 [doi]
• Reminiscing through 40 years of CMOS analog circuit design: from audio to GHzRinaldo Castello. 25-32 [doi]
• From Less Batteries to Battery-Less: Enabling A Greener World through Ultra-Wide Power-Performance Adaptation down to pWsMassimo Alioto. 33-40 [doi]
• Innovations for Intelligent EdgeVida Ilderem, Stefano Pellerano, Jim Tschanz, Tanay Karnik, Vivek De. 41-44 [doi]
• Coupling control in the few-electron regime of quantum dot arrays using 2-metal gate levels in CMOS technologyBruna Cardoso Paz, Victor El-Homsy, David J. Niegemann, Bernhard Klemt, Emmanuel Chanrion, Vivien Thiney, Baptiste Jadot, Pierre-André Mortemousque, Benoit Bertrand, Thomas Bedecarrats, Heimanu Niebojewski, François Perruchot, Silvano De Franceschi, Maud Vinet, Matias Urdampilleta, Tristan Meunier. 45-48 [doi]
• Multi-Gate FD-SOI Single Electron Transistor for hybrid SET-MOSFET quantum computingFabio Bersano, Franco De Palma, Fabian Oppliger, Floris Braakman, Ionut Radu, Pasquale Scarlino, Martino Poggio, Adrian Mihai Ionescu. 49-52 [doi]
• Cryogenic Comparator Characterization and Modeling for a Cryo-CMOS 7b 1-GSa/s SAR ADCGerd Kiene, Aishwarya Gunaputi Sreenivasulu, Ramon Overwater, Masoud Babaie, Fabio Sebastiano. 53-56 [doi]
• A cryogenic SRAM based arbitrary waveform generator in 14 nm for spin qubit controlMridula Prathapan, Peter Mueller, Christian Menolfi, Matthias Brändli, Marcel A. Kossel, Pier Andrea Francese, David Heim, Maria Vittoria Oropallo, Andrea Ruffino, Cezar B. Zota, Thomas Morf. 57-60 [doi]
• A 28nm 6.5-8.1GHz 1.16mW/qubit Cryo-CMOS System-an-Chip for Superconducting Qubit ReadoutSteven Van Winckel, Alican Çaglar, Benjamin Gys, Steven Brebels, Anton Potocnik, Bertrand Parvais, Piet Wambacq, Jan Craninckx. 61-64 [doi]
• Non-Volatile Ternary Content Addressable Memory based on Phase Change Nanoelectromechanical (NEM) RelayMohammad Ayaz Masud, Luis Hurtado, Gianluca Piazza. 65-68 [doi]
• A 24V Thin-Film Ultrasonic Driver for Haptic Feedback in Metal-Oxide Thin-Film Technology using Hybrid DLL Locking ArchitectureJonas Pelgrims, Kris Myny, Wim Dehaene. 69-72 [doi]
• A monolithic SPAD-based random number generator for cryptographic applicationNicola Massari, Alessandro Tontini, Luca Parmesan, Matteo Perenzoni, Milos Gruijé, Ingrid Verbauwhede, Thomas Strohm, Dayo Oshinubi, Ingo Herrmann, Andreas Brenneis. 73-76 [doi]
• Quantum-Correlated Photon-Pair Source with Integrated Feedback Control in 45 nm CMOSDanielius Kramnik, Imbert Wang, Josep M. Fargas Cabanillas, Anirudh Ramesh, Sidney Buchbinder, Panagiotis Zarkos, Christos Adamopoulos, Prem Kumar, Milos A. Popovic, Vladimir Stojanovic. 77-80 [doi]
• A 4.6-8.3 TOPS/W 1.2-4.9 TOPS CNN-based Computational Imaging Processor with Overlapped Stripe Inference Achieving 4K Ultra-HD 30fpsYu-Chun Ding, Kai-Pin Lin, Chi-Wen Weng, Li-Wei Wang, Huan-Ching Wang, Chun-Yeh Lin, Yong-Tai Chen, Chao-Tsung Huang. 81-84 [doi]
• 2 Self-Attention Processor with Sign Random Projection-based ApproximationSeong Hoon Seo, Soosung Kim, Sung Jun Jung, Sangwoo Kwon, Hyunseung Lee, Jae W. Lee. 85-88 [doi]
• A 28nm 8-bit Floating-Point Tensor Core based CNN Training Processor with Dynamic Activation/Weight SparsificationShreyas Kolala Venkataramanaiah, Jian Meng, Han-Sok Suh, Injune Yeo, Jyotishman Saikia, Sai Kiran Cherupally, Yichi Zhang, Zhiru Zhang, Jae-sun Seo. 89-92 [doi]
• A Differentiable Neural Computer for Logic Reasoning with Scalable Near-Memory Computing and Sparsity Based EnhancementYuhao Ju, Shiyu Guo, Zixuan Liu, Tianyu Jia, Jie Gu 0001. 93-96 [doi]
• 2 CNN Accelerator with Spatially Independent Fusion for Real-Time UHD Super-ResolutionSumin Lee, Ki-Beom Lee, Sunghwan Joo, Hong Keun Ahn, Junghyup Lee, Dohyung Kim, Bumsub Ham, Seong-Ook Jung. 97-100 [doi]
• A 40nm RRAM Compute-in-Memory Macro with Parallelism-Preserving ECC for Iso-Accuracy Voltage ScalingWantong Li, James Read, Hongwu Jiang, Shimeng Yu. 101-104 [doi]
• In-memory Realization of In-situ Few-shot Continual Learning with a Dynamically Evolving Explicit MemoryGeethan Karunaratne, Michael Hersche, Jovin Langenegger, Giovanni Cherubini, Manuel Le Gallo, Urs Egger, Kevin Brew, Samuel Choi, Injo Ok, Mary Claire Silvestre, Ning Li, Nicole Saulnier, Victor Chan, Ishtiaq Ahsan, Vijay Narayanan, Luca Benini, Abu Sebastian, Abbas Rahimi. 105-108 [doi]
• An embedded PCM Peripheral Unit adding Analog MAC In-Memory Computing Feature addressing Non-linearity and Time Drift CompensationAlessio Antolini, Andrea Lico, Eleonora Franchi Scarselli, Antonio Gnudi, Luca Perilli, Mattia Luigi Torres, Marcella Carissimi, Marco Pasotti, Roberto Canegallo. 109-112 [doi]
• A Highly Integrated Crosspoint Array Using Self-rectifying FTJ for Dual-mode Operations: CAM and PUFSehee Lim, Youngin Goh, Young Kyu Lee, Dong Han Ko, Junghyeon Hwang, Minki Kim, Yeongseok Jeong, Hunbeom Shin, Sanghun Jeon, Seong-Ook Jung. 113-116 [doi]
• Physical Implementation of a Tunable Memristor-based Chua's CircuitManuel Escudero, Sabina Spiga, Mauro Di Marco, Mauro Forti, Giacomo Innocenti, Alberto Tesi, Fernando Corinto, Stefano Brivio. 117-120 [doi]
• Ferroelectric Schottky Barrier MOSFET as Analog Synapses for Neuromorphic ComputingFengben Xi, Andreas Grenmy, Jiayuan Zhang, Yi Han, Jin Hee Bae, Detlev Grützmacher, Qing-Tai Zhao. 121-124 [doi]
• Interplay between charge trapping and polarization switching in MFDM stacks evidenced by frequency-dependent measurementsJustine Barbot, Jean Coignus, Nicolas Vaxelaire, Catherine Carabasse, Olivier Glorieux, Messaoud Bedjaoui, François Aussenac, François Andrieu, François Triozon, Laurent Grenouillet. 125-128 [doi]
• Frequency modulation of conductance level in PCM device for neuromorphic applicationsA. Trabelsi, Carlo Cagli, Tifenn Hirtzlin, Olga Cueto, Marie-Claire Cyrille, Elisa Vianello, V. Meli, Veronique Sousa, Guillaume Bourgeois, François Andrieu. 129-132 [doi]
• 2-based RRAM for parameter extraction and neuromorphic engineeringAlessandro Milozzi, Daniel Reiser, Andreas Drost, Thomas Neuner, Marc Tornow, Daniele Ielmini. 133-136 [doi]
• Improvement of FTJ on-current by work function engineering for massive parallel neuromorphic computingSuzanne Lancaster, Quang T. Duong, Erika Covi, Thomas Mikolajick, Stefan Slesazeck. 137-140 [doi]
• A 28nm 1.644TFLOPS/W Floating-Point Computation SRAM Macro with Variable Precision for Deep Neural Network Inference and TrainingSangsu Jeong, Jeongwoo Park, Dongsuk Jeon. 145-148 [doi]
• All-Digital Time-Domain Compute-in-Memory Engine for Binary Neural Networks With 1.05 POPS/W Energy EfficiencyJie Lou, Christian Lanius, Florian Freye, Tim Stadtmann, Tobias Gemmeke. 149-152 [doi]
• A 1.23-GHz 16-kb Programmable and Generic Processing-in-SRAM Accelerator in 65nmAmitesh Sridharan, Shaahin Angizi, Sai Kiran Cherupally, Fan Zhang, Jae-sun Seo, Deliang Fan. 153-156 [doi]
• A 1-to-4b 16.8-POPS/W 473-TOPS/mm2 6T-based In-Memory Computing SRAM in 22nm FD-SOI with Multi-Bit Analog Batch-NormalizationAdrian Kneip, Martin Lefebvre, Julien Verecken, David Bol. 157-160 [doi]
• Fully integrated Si: HfO2 Negative Capacitance 2D-2D WSe2/SnSe2 Subthermionic Tunnel FETsSadegh Kamaei, Ali Saeidi, Xia Liu, Carlotta Gastaldi, Clara Moldovan, Jürgen Brugger, Adrian M. Ionescu. 161-164 [doi]
• y pin-Diodes Grown on a GeSn BufferLukas Seidel, Sören Schäfer, Michael Oehme, Dan Buca, Giovanni Capellini, Jörg Schulze, Daniel Schwarz. 165-168 [doi]
• GeSn-on-Si Avalanche Photodiodes for Short-Wave Infrared DetectionMaurice Wanitzek, Michael Oehme, Christian Spieth, Daniel Schwarz, Lukas Seidel, Jörg Schulze. 169-172 [doi]
• A Drift-Compensated Magnetic Spectrometer for Point-of-Care Wash-Free Immunoassays using a Concurrent Dual-Frequency OscillatorJui-Hung Sun, Bill Ling, Md. Abdullah-Al Kaiser, Constantine Sideris. 173-176 [doi]
• A Full Current-Mode Timing Circuit with Dark Noise Suppression for the CERN CMS ExperimentEdgar Albuquerque, Ricardo Bugalho, L. B. Oliveira, T. Niknejad, José C. Silva, Alessio Boletti, João Varela. 177-180 [doi]
• 2 Temperature Sensor with On-chip Gain and Offset CorrectionYuting Shen, Mariska van der Struijk, Kevin Pelzers, Hanyue Li, Eugenio Cantatore, Pieter Harpe. 181-184 [doi]
• An Integrated Optical Transceiver Circuit for Power Delivery and Bi-directional Data Communication in a Medical Catheter DeviceAlexander Frank, Jens Anders, Joachim N. Burghartz, Bart Kootte, Jean Schleipen, Peter Jutte. 185-188 [doi]
• A reconfigurable 224×272-pixel single-photon image sensor for photon timestamping, counting and binary imaging at 30.0-μm pitch in 11 0nm CIS technologyLeonardo Gasparini, Manuel Moreno-García, Majid Zarghami, André Stefanov, Bruno Eckmann, Matteo Perenzoni. 189-192 [doi]
• Statistical measurements and Monte-Carlo simulations of DCR in SPADsMathieu Sicre, Megan Agnew, Christel Buj, Caroline Coutier, Dominique Golanski, Rémi Helleboid, Bastien Mamdy, Isobel Nicholson, Sara Pellegrini, Denis Rideau, David Roy 0001, Francis Calmon. 193-196 [doi]
• A scalable 64×64 pixels monolithic HV-CMOS sensor for hadron therapy with 1ns time stamping capability and in-pixel ADCNicola Massari, Alessio D'Andragora, Matteo Perenzoni, Andrey Selijak, Carlos Chavez Barajas, Alan Taylor, Jon Taylor, Gianluigi Casse, John Pettingell, Ignacio Di Biase. 197-200 [doi]
• A 32-ch Neuromodulator with redundant Voltage Monitors avoiding Blocking CapacitorsStefan Reich, Markus Sporer, Joachim Becker, Stefan B. Rieger, Martin Schüttler, Maurits Ortmanns. 201-204 [doi]
• Fully Implantable 192×256 SPAD Sensor with Global-Shutter and Micro-LEDs for Bidirectional Subdural Optical Brain-Computer InterfacesEric H. Pollmann, Yatin Gilhotra, Heyu Yin, Kenneth L. Shepard. 205-208 [doi]
• 3 ADC-less Neural Implant SoC utilizing 13.2pJ/Sample Time-domain Bi-phasic Quasi-static Brain Communication with Direct Analog to Time ConversionBaibhab Chatterjee, K. Gaurav Kumar, Shulan Xiao, Gourab Barik, Krishna Jayant, Shreyas Sen. 209-212 [doi]
• A 50 Mb/s Full HBC TRX with Adaptive DFE and Variable-Interval 3x Oversampling CDR in 28nm CMOS Technology for A 75 cm Body Channel Moving at 0.75 Cycle/secJaehyun Ko 0001, Iksu Jang, Chanho Kim, JiHoon Park, Changjae Moon, Sooeun Lee, Byungsub Kim. 213-216 [doi]
• An Implantable Power Extraction Circuit with Integrated PMUTs for Wireless Power DeliveryOi-Ying Wong, Dries Tabruyn, Veronique Rochus, Nick Van Helleputte. 217-220 [doi]
• A PMUT Transceiver Front-End with 100-V TX Driver and Low-Noise Voltage Amplifier in BCD-SOI TechnologyLara Novaresi, Piero Malcovati, Andrea Mazzanti, Edoardo Bonizzoni, Marco Terenzi, Stefano Ottaviani, Davide Ghisu, Fabio Quaglia, Alessandro Stuart Savoia. 221-224 [doi]
• 3Image ResolutionDaniel Krüger, Aoyang Zhang, Henry Hinton, Victor M. Arnal, Yi-Qiao Song, Yiqiao Tang, Ka-Meng Lei, Jens Anders, Donhee Ham. 225-228 [doi]
• A Sub-0.01° Phase Resolution 6.8-mW fNIRS Readout Circuit Employing a Mixer-First Frequency-Domain ArchitectureCheng Chen, Zhouchen Ma, Yaxin Liu, Zhenhong Liu, Linfeng Zhou, Yan Wu, Liang Qi, Yongfu Li 0002, Mohamad Sawan, Guoxing Wang, Jian Zhao 0004. 229-232 [doi]
• divHongzhuo Liu, Wei Deng 0001, Haikun Jia, Shiyan Sun, Qixiu Wu, Jiajie Tang, Zhihua Wang 0001, Baoyong Chi. 233-236 [doi]
• A Bang-Bang Digital PLL Covering 11.1-14.3 GHz and 14.7-18.7 GHz with sub-40 fs RMS Jitter in 7 nm FinFET TechnologyStaffan Ek, Patrik Karlsson, Andreas Kämpe, Roland Strandberg, Aravind Tharayil Narayanan, Martin Anderson, Hind Dafallah, Mesrop Daghbashyan, Tayebeh Ghanavati Nejad, Robert Hägglund, Nikola Ivanisevic, Robert Nilsson, Peter Nygren, Mattias Palm, Erik Säll, Sha Tao, My-Chien Yee, Lars Sundström. 237-240 [doi]
• A 2.5 GHz 104 mW 57.35 dBc SFDR Non-linear DAC-based Direct-Digital Frequency Synthesizer in 65 nm CMOS ProcessDong Hyun Yoon, Kwang-Hyun Baek, Tony Tae-Hyoung Kim. 241-244 [doi]
• An Inductorless Fractional-N PLL Using Harmonic-Mixer-Based Dual Feedback and High-OSR Delta-Sigma-Modulator with Phase-Domain FilteringMasaru Osada, Zule Xu, Tetsuya Iizuka. 245-248 [doi]
• A -247.1 dB FoM, -77.9dBc Reference Spur Ring-Oscillator-Based Injection-Locked Clock Multiplier with Multi-Phase-Based CalibrationYeonggeun Song, Kyoungjoon Ha, Han-Gon Ko, Min-Seong Choo, Deog Kyoon Jeong. 249-252 [doi]
• A 590 µW, 106.6 dB SNDR, 24 kHz BW Continuous-Time Zoom ADC with a Noise-Shaping 4-bit SAR ADCShubham Mehrotra, Efraïm Eland, Shoubhik Karmakar, Angqi Liu, Burak Gönen, Muhammed Bolatkale, Robert H. M. van Veldhoven, Kofi A. A. Makinwa. 253-256 [doi]
• A 150 mV, Sub-1 nW, 0.75%-Full-Scale INL Delta-Sigma ADC for Power-Autonomous Sensor NodesAlessandro Catania, Andrea Ria, Giuseppe Manfredini, Michele Dei, Massimo Piotto, Paolo Bruschi. 257-260 [doi]
• A 10.4-ENOB 0.92-5.38 μW Event-Driven Level-Crossing ADC with Adaptive Clocking for Time-Sparse Edge ApplicationsJonah Van Assche, Georges G. E. Gielen. 261-264 [doi]
• SmartHeaP - A High-level Programmable, Low Power, and Mixed-Signal Hearing Aid SoC in 22nm FD-SOIJens Karrenbauer, Simon C. Klein, Sven Schönewald, Lukas Gerlach, Meinolf Blawat, Jens Benndorf, Holger Blume. 265-268 [doi]
• A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoCTianyu Jia, Paolo Mantovani, Maico Cassel dos Santos, Davide Giri, Joseph Zuckerman, Erik Jens Loscalzo, Martin Cochet, Karthik Swaminathan, Gabriele Tombesi, Jeff Jun Zhang, Nandhini Chandramoorthy, John-David Wellman, Kevin Tien, Luca P. Carloni, Kenneth L. Shepard, David Brooks 0001, Gu-Yeon Wei, Pradip Bose. 269-272 [doi]
• Darkside: 2.6GFLOPS, 8.7mW Heterogeneous RISC-V Cluster for Extreme-Edge On-Chip DNN Inference and TrainingAngelo Garofalo, Matteo Perotti, Luca Valente, Yvan Tortorella, Alessandro Nadalini, Luca Benini, Davide Rossi, Francesco Conti 0001. 273-276 [doi]
• A 91.6% Peak Efficiency Time-Domain-Controlled Single-Inductor Triple-Output Step-Up Converter with ±7.5 to ±12V Bipolar Output VoltagesPeng Cao, Danzhu Lu, Jiawei Xu 0001, Xiaoyang Zeng, Zhiliang Hong. 277-280 [doi]
• An Automotive-Use Dual-fsw-Zone Hybrid Switching Power Converter with Vo-Jitter-Immune Spread-Spectrum ModulationJin Woong Kwak, D. Brian Ma. 281-284 [doi]
• A Galvanic-Free Secondary-Side Control Flyback Converter with Digital Adaptive On-Time Control and Direct Sequence Spread Spectrum Technique for 15.5% Error Recovery Rate ImprovementWei-Cheng Huang, Yuan-Jin Li, Yi-Hsiang Kao, Ke-Horng Chen, Kuo-Lin Zheng, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai. 285-288 [doi]
• A Half-Bridge Gate-Driver for high-efficient Boost Converter Applications with single-sided ZVS and an adaptive Ringing Suppression TechniqueMichael Hanhart, Jonas Zoche, Jan Grobe, Léon Weihs, Leo Rolff, Ralf Wunderlich, Stefan Heinen. 289-292 [doi]
• A 4 to 40V Wide Input Range and Energy Re-Cycling High Power LiDAR Driver for 5% Efficiency Enhancement and 300m Long-distance Object DetectionSi-Yi Li, Zheng-Lun Huang, Sheng-Cheng Lee, Ke-Horng Chen, Kuo-Lin Zheng, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai. 293-296 [doi]
• High-Voltage CMOS RF Switch with Active BiasingValentyn Solomko, Semen Syroiezhin, Danial Tayari, Jochen Essel, Robert Weigel. 297-300 [doi]
• Switching Time Acceleration for High-Voltage CMOS RF SwitchSemen Syroiezhin, Oguzhan Oezdamar, Robert Weigel, Valentyn Solomko. 301-304 [doi]
• A Low-Loss 77 GHz Sub-Sampling Passive Mixer Integrated in a 28-nm CMOS Radar ReceiverAlexandre Flete, Christophe Viallon, Philippe Cathelin, Thierry Parra. 305-308 [doi]
• An FDD Auxiliary Receiver with a Highly Linear Low Noise AmplifierJin Jin, Simone Lecchi, Rinaldo Castello, Danilo Manstretta. 309-312 [doi]
• A 433-MHz Wireless Burst-Chirp Modulation Transmitter with Adaptive Duty-Cycle Control and Precharge MechanismJing Siang Chen, Chun-Ting Chang, Yu-Te Liao. 313-316 [doi]
• A Pipeline ADC with Negative C-assisted SC Amplifier Canceling Gain Error and NonlinearityWoojin Jang, Gyeong-Gu Kang, Yong Lim, Hyun-Sik Kim. 317-320 [doi]
• A 2GHz 2-bit Continuous-Time Delta Sigma ADC with 2GHz chopper achieving 12nV/sqrt(Hz) 1/f noise at 153kHz and -104.7dBc THD in 30MHz BWPierluigi Cenci, Hans Brekelmans, Shagun Bajoria, Marcello Ganzerli, Bernard Burdiek, Robert Rutten, Yihan Gao, Muhammed Bolatkale, Paul Swinkels, Lucien J. Breems. 321-324 [doi]
• 6GS/s 8-channel CIC SAR TI-ADC with Neural Network CalibrationEvelyn Ware, Justin Correll, Seungjong Lee, Michael Flynn. 325-328 [doi]
• 2 4x Delta-Interleaved Switched-Capacitor DAC in 16nm FinFET CMOSPietro Caragiulo, Athanasios Ramkaj, Amin Arbabian, Boris Murmann. 329-332 [doi]
• A 28GHz Area-Efficient CMOS Vector-Summing Phase Shifter Utilizing Phase-Inverting Type-I Poly-Phase Filter for 5G New RadioMinzhe Tang, Yi Zhang 0092, Jian Pang, Atsushi Shirane, Kenichi Okada. 333-336 [doi]
• avg in 0.13 μm SiGe for 400 MHz BW 5G NRHao Gao, Sina Mortezazadeh Mahani, David Seebacher, Matteo Bassi, Gernot Hueber. 337-340 [doi]
• A 24-to-44 GHz Compact Linear 5G Power Amplifier with Open-Terminated Balun in 65nm Bulk CMOSKyutaek Oh, Hyunjin Ahn, Ilku Nam, Ockgoo Lee. 341-344 [doi]
• A CMOS Full-Wave Switching Rectifier with Frequency Up-Down Conversion for 5G NR Wirelessly-Powered Relay TransceiversSena Kato, Keito Yuasa, Michihiro Ide, Atsushi Shirane, Kenichi Okada. 345-348 [doi]
• INTIACC: A 32-bit Floating-Point Programmable Custom-ISA Accelerator for Solving Classes of Partial Differential EquationsPaul Xuanyuanliang Huang, Daniel Jang, Yannis P. Tsividis, Mingoo Seok. 349-352 [doi]
• A Scalable Bit-Serial Computing Hardware Accelerator for Solving 2D/3D Partial Differential Equations Using Finite Difference MethodJunjie Mu, Chengshuo Yu, Tony Tae-Hyoung Kim, Bongjin Kim. 353-356 [doi]
• A 283 pJ/b 240 Mb/s Floating-Point Baseband Accelerator for Massive MU-MIMO in 22FDXOscar Castañeda, Luca Benini, Christoph Studer. 357-360 [doi]
• A Wide-input-range 918MHz RF Energy Harvesting IC with Adaptive Load and Input Power Tracking TechniqueJing-Ren Yan, Hao-Yi Kuo, Yu-Te Liao. 361-364 [doi]
• Input Nonlinear Adaptive Voltage Position Technique in the Switched-capacitor Converter with Feedforward Compensation for 87.8% Peak Efficiency under 8X Input InterferenceShu-Yung Lin, Sheng-Cheng Lee, Ke-Horng Chen, Kuo-Lin Zheng, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai. 365-368 [doi]
• A 385mV, 270nW, Accurate Voltage Level Detector for IoTOmer Nechushtan, Asaf Feldman, Joseph Shor. 369-372 [doi]
• An Extended Temperature Range ePCM Memory in 90-nm BCD for Smart Power ApplicationsMarcella Carissimi, Chantal Auricchio, Emanuela Calvetti, Laura Capecchi, M. Torres, Stefano Zanchi, P. Gupta, Riccardo Zurla, Alessandro Cabrini, Daniele Gallinari, Fabio Disegni, Massimo Borghi, E. Palumbo, Andrea Redaelli, Marco Pasotti. 373-376 [doi]
• On-Chip High-Resolution Timing Characterization Circuits for Memory IPsAmit Agarwal 0001, Steven Hsu, Mark A. Anders 0001, Gunjan Pandya, Ram Krishnamurthy 0001, James W. Tschanz, Vivek De. 377-380 [doi]
• Capacitance-Based Voltage Regulation- and Reference-Free Temperature-to-Digital Converter down to 0.3 V and 2.5 nW for Direct HarvestingOrazio Aiello, Massimo Alioto. 381-384 [doi]
• A 24 GHz Quadrature VCO Based on Coupled PLL with -134 dBc/Hz Phase Noise at 10 MHz Offset in 28 nm CMOSAgata Iesurum, Davide Manente, Fabio Padovan, Matteo Bassi, Andrea Bevilacqua. 385-388 [doi]
• A K-band Gilbert-Cell Frequency Doubler with Self-Adjusted 25% LO Duty-Cycle in SiGe BiCMOS TechnologyLorenzo Piotto, Guglielmo De Filippi, Daniele Dal Maistro, Simone Erba, Andrea Mazzanti. 389-392 [doi]
• A 1.8-67GHz Divide-by-4 ILFD Using Area-Efficient Transformer-Based Injection-Enhancing TechniqueYudai Yamazaki, Jian Pang, Atsushi Shirane, Kenichi Okada. 393-396 [doi]
• A Fully Differential 40 MHz Switched-Capacitor Crystal Oscillator with Fast Start-UpWim Kruiskamp. 397-400 [doi]
• A 128ksps 120dB THD Low Noise Analog Front EndGerard Mora-Puchalt, Gabriel Banarie, Pawel Czapor, Adrian Sherry, Roberto Maurino, Jesús Bonache, Italo Medina. 401-404 [doi]
• 2, 0.4V-VDD, 4.5nW-Power DC-Coupled Digital Acquisition Front-End Based on Time-Multiplexed Digital Differential AmplificationPaolo Crovetti, Roberto Rubino, Pedro Toledo, Francesco Musolino, Hamilton Klimach, Yong Chen 0005, Anna Richelli. 405-408 [doi]
• A 69dBA-730µW Silicon Microphone System with Ultra & Infra-Sound RobustnessJose Luis Ceballos, Christopher Rogi, Fulvio Ciciotti, Cesare Buffa, Dietmar Straeussnigg, Andreas Wiesbauer. 409-412 [doi]
• A Nonuniform Sampling Lifetime Estimation Technique for Luminescent Oxygen MeasurementsIan Costanzo, Devdip Sen, John McNeill, Ulkuhan Guler. 413-416 [doi]
• A 2.4GHz Full-Duplex Transceiver with Broadband (+120MHz), Linearity-Calibrated and Long-Delayed Self-Interference CancellationXichen Li, Yi-Hsiang Huang, Fucheng Yin, Jacques C. Rudell. 417-420 [doi]
• A 3-10GHz 21.5mW/Channel RX and 8.9mW TX IR-UWB 802.15.4a/z 1T3R TransceiverElbert Bechthum, Minyoung Song, Gaurav Singh 0005, Erwin Allebes, Charis Basetas, Pepijn Boer, Arjan Breeschoten, Stefan Cloudt, Johan Dijkhuis, Ming Ding 0003, Sherwin Gatchalian, Yuming He, Johan H. C. van den Heuvel, Martijn Hijdra, Paul Mateman, Bernard Meyer, Gert-Jan van Schaik, Mohieddine El Soussi, Bart Thijssen, Stefano Traferro, Evgenii Turin, Peter Vis, Nick Winkel, Peng Zhang, Yao-Hong Liu, Christian Bachmann. 421-424 [doi]
• A 58 GHz Bandwidth, and less than 1.8% THD, Mach-Zehnder Driver, in 28 nm CMOS TechnologyNicola Cordioli, Danilo Manstretta, Rinaldo Castello. 429-432 [doi]
• A 136GΩ-Input-Impedance Active Electrode for Non-Contact ECG Using Auto-Calibrated Positive Feedback and Capacitance Scaling in Femtofarad ResolutionPeizhuo Wang, Tianxiang Qu, Liangbo Lei, Zhiliang Hong, Jiawei Xu 0001. 433-436 [doi]
• A Chopper Biopotential Instrumentation Amplifier With DSL-Embedded Input Stage Achieving 109 dB CMRR and 400 mV DC Offset ToleranceSurachoke Thanapitak, Chutham Sawigun. 437-440 [doi]
• A Direct Sensor Readout Circuit Using VCO-Driven Chopping with 42dB SNR at 800µVpp InputYingjie Chen, Marino De Jesus Guzman, Beomsoo Park, Nima Maghari. 441-444 [doi]
• Mixed-Signal Compensation of Tripolar Cuff Electrode Imbalance in a Low-Noise ENG Analog Front-EndRémi Dekimpe, David Bol. 445-448 [doi]
• A Full D-band Multi-Gbit RF-DAC in 90 nm SiGe BiCMOS based on Passive Vector AggregationTim Maiwald, Akshay Visweswaran, Klaus Aufinger, Robert Weigel. 449-452 [doi]
• sat, 16.5% PAE in 22-nm CMOS FD-SOIJeff Shih-Chieh Chien, James F. Buckwalter. 453-456 [doi]
• A D-Band mm-wave spectroscopy TX and RX in 28 nm CMOS with 15.6 dBm EIRP and 17.1 dB NF with integrated antennasGabriel Guimaraes, Patrick Reynaert. 457-460 [doi]
• A Joint Space/Time Modulation Lens-Coupled 230-GHz Terahertz Source with 40°/43°2-D Beam Steering for Fast High-Resolution Imaging/Sensing ApplicationsHossein Jalili, Yuqi Liu, Tzu-Yuan Huang, Hua Wang. 461-464 [doi]
• A 0.9-nA Temperature-Independent 565-ppm/°C Self-Biased Current Reference in 22-nm FDSOIMartin Lefebvre, Denis Flandre, David Bol. 469-472 [doi]
• A Compact 2.5-nJ Energy/Conversion NPN-Based Temperature-to-Digital Converter with a Fully Current-Mode Processing ArchitectureAntonio Aprile, Michele Folz, Daniele Gardino, Piero Malcovati, Edoardo Bonizzoni. 473-476 [doi]
• A 5.4-mW 50-MHz 29.3-dBm-IIP3 Fourth-Order Low-Pass FilterLiangbo Lei, Cong Tao, Zhipeng Chen, Zhiliang Hong, Yumei Huang. 477-480 [doi]
• A 135 GHz 32 Gb/s Direct-Digital Modulation 16-QAM Transmitter in 28 nm CMOSCarl D'heer, Patrick Reynaert. 481-484 [doi]
• A 135 GHz 24 Gb/s Direct-Digital Demodulation 16-QAM Receiver in 28 nm CMOSCarl D'heer, Patrick Reynaert. 485-488 [doi]
• A Low-Power and Energy-Efficient D-Band CMOS Four-Channel Receiver with Integrated LO Generation for Digital Beamforming ArraysEthan Chou, Nima Baniasadi, Hesham Beshary, Meng Wei, Emily Naviasky, Lorenzo Iotti, Ali M. Niknejad. 489-492 [doi]
• A Reconfigurable Digital Beamforming V-Band Phased-Array ReceiverDeniz Dosluoglu, Kun-Da Chu, Diego Peña-Colaiocco, Ivan Zhao, Visvesh Sathe 0001, Jacques C. Rudell. 493-496 [doi]
• A 112-Gb/s Single-Ended PAM-4 Transceiver Front-End for Reach Extension in Long-Reach LinkXiongshi Luo, Xuewei You, Jiahan Fu, Zhenghao Li, Liping Zhong, Taiyang Fan, Zhang Qiu, Wenbo Xiao, Yong Chen, Quan Pan 0002. 497-500 [doi]
• A 2×50Gb/s Single-Ended MIMO PAM-4 Crosstalk Cancellation and Signal Reutilization Receiver in 28 nm CMOSLiping Zhong, Hongzhi Wu, Weitao Wu, Wenbo Xiao, Xiongshi Luo, Dongfan Xu, Xuxu Cheng, Zhenghao Li, Taiyang Fan, Quan Pan 0002. 501-504 [doi]
• A 56-Gb/s PAM4 Transceiver with False-Lock-Aware Locking Scheme for Mueller-Müller CDRFumihiko Tachibana, Huy Cu Ngo, Go Urakawa, Takashi Toi, Mitsuyuki Ashida, Yuta Tsubouchi, Mai Nozawa, Junji Wadatsumi, Hiroyuki Kobayashi, Jun Deguchi. 505-508 [doi]
• A 64Gb/s Downlink and 32Gb/s Uplink NRZ Wireline Transceiver with Supply Regulation, Background Clock Correction and EOM-based Channel Adaptation for Mid-Reach Cellular Mobile Interface in 8nm FinFETSoo-Min Lee, Jihoon Lim, Jaehyuk Jang, HyoungJoong Kim, Kyunghwan Min, Woongki Min, Hyeonji Han, Gyusik Kim, Jaeyoung Kim, Chulho Kim, Sejun Jeon, Jinhoon Park, Hyunsu Chae, Sangwook Han, Hiep Pham, Xingliang Zhao, Qilin Gu, Chih-Wei Yao, Sangho Kim, Jongwoo Lee. 509-512 [doi]
• A 2.17-pJ/b 5b-Response Attack-Resistant Strong PUF with Enhanced Statistical PerformanceKunyang Liu, Gen Li, Zihan Fu, Xuanzhen Wang, Hirofumi Shinohara. 513-516 [doi]
• 2 Gate Leakage-Based Physically Unclonable Function With Area Efficient Current Tilting-Based Masking SchemeBeomsoo Park, Nima Mazhari. 517-520 [doi]
• Logic-embedded Physically Unclonable Functions for Synthesizable and Periphery-free Implementation for Low Area and Design Cost IoT SecuritySeonho Kim, Changyoun Im, Jongmin Lee, Soyoun Jeong, Jaerok Kim, Yoonmyung Lee. 521-524 [doi]
• Configurable Energy-Efficient Lattice-Based Post-Quantum Cryptography Processor for IoT DevicesByungjun Kim, Jaehan Park, SeungHyun Moon, Kiseo Kang, Jae-Yoon Sim. 525-528 [doi]
• Fine-Grained Electromagnetic Side-Channel Analysis Resilient Secure AES Core with Stacked Voltage Domains and Spatio-temporally Randomized Circuit BlocksMeizhi Wang, Sirish Oruganti, Shanshan Xie, Raghavan Kumar, Sanu Mathew, Jaydeep P. Kulkarni. 529-532 [doi]
• A Review on the State-of-the-Art THz FMCW Radars Implemented on Silicon: InvitedMorteza Tavakoli Taba, S. M. Hossein Naghavi, Ehsan Afshari. 533-537 [doi]
• Integrated Optical Phased Arrays on SiliconFarshid Ashtiani, Firooz Aflatouni. 538-541 [doi]
• Full-Duplex Wireless for (Joint-) Communication and SensingHany Abolmagd, Raghav Subbaraman, Dinesh Bharadia, Sudip Shekhar. 542-545 [doi]
• Reconfigurable Intelligent Surfaces Enabled by Silicon Chips for Secure and Robust mmWave and THz Wireless CommunicationKaushik Sengupta, Suresh Venkatesh, Hooman Saeidi, Xuyang Lu. 546-549 [doi]
• A 130μW Three-Step DT Incremental Δ ∑ ADC Achieving 107.6dB DR and 99.3dB SNDR with Zoom and Extended-Range CountingLairong Fang, Yijie Li, Yao Zhang, Shuwen Zhang, Xiaoyang Zeng, Zhiliang Hong, Jiawei Xu 0001. 554-557 [doi]