Adrian Kneip - researchr alias

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Viewing Publication 1 - 5 from 5

2023

2 CIM-SRAM With Multi-Bit Analog Batch-NormalizationAdrian Kneip, Martin Lefebvre 0002, Julien Verecken, David Bol. jssc, 58(7):1871-1884, 2023. [doi]

A 7T-NDR Dual-Supply 28-nm FD-SOI Ultra-Low Power SRAM With 0.23-nW/kB Sleep Retention and 0.8 pJ/32b Access at 64 MHz With Forward Back BiasAdrian Kneip, David Bol. tcasI, 70(3):1311-1323, March 2023. [doi]

2022

A 1-to-4b 16.8-POPS/W 473-TOPS/mm2 6T-based In-Memory Computing SRAM in 22nm FD-SOI with Multi-Bit Analog Batch-NormalizationAdrian Kneip, Martin Lefebvre, Julien Verecken, David Bol. esscirc 2022: 157-160 [doi]

2021

SleepRider: a 5.5μW/MHz Cortex-M4 MCU in 28nm FD-SOI with ULP SRAM, Biomedical AFE and Fully-Integrated Power, Clock and Back-Bias ManagementRémi Dekimpe, Maxime Schramme, Martin Lefebvre, Adrian Kneip, Roghayeh Saeidi, Mathieu Xhonneux, Ludovic Moreau, Marco Gonzalez, Thibault Pirson, David Bol. vlsic 2021: 1-2 [doi]

Impact of Analog Non-Idealities on the Design Space of 6T-SRAM Current-Domain Dot-Product Operators for In-Memory ComputingAdrian Kneip, David Bol. tcasI, 68(5):1931-1944, 2021. [doi]

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