Dawei Ye - researchr alias

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Viewing Publication 1 - 20 from 20

2023

Echo State Network-Enabled Intelligent Smart Sensor Design for Creating a Robotic Nervous SystemDawei Ye, Bingxin Cao, Weiping Zhou. ijprai, 37(7), June 2023. [doi]

2022

2021

2020

A 340 nW/Channel 110 dB PSRR Neural Recording Analog Front-End Using Replica-Biasing LNA, Level-Shifter Assisted PGA, and Averaged LFP Servo Loop in 65 nm CMOSLiangjian Lyu, Dawei Ye, C.-J. Richard Shi. tbcas, 14(4):811-824, 2020. [doi]

A Fully-Integrated 64-Channel Wireless Neural Interfacing SoC Achieving 110 dB AFE PSRR and Supporting 54 Mb/s Symbol Rate, Meter-Range Wireless Data TransmissionLiangjian Lyu, Dawei Ye, Rongjin Xu, Geng Mu, Heng Zhao, Yingfei Xiang, Yuting Tu, Yiyun Zhang, C.-J. Richard Shi. tcas, 67-II(5):831-835, 2020. [doi]

A 400 MHz, 8-Bit, 1.75-ps Resolution Pipelined-Two-Step Time-to-Digital Converter with Dynamic Time AmplificationYuting Tu, Rongjin Xu, Dawei Ye, Liangjian Lyu, C.-J. Richard Shi. iscas 2020: 1-4 [doi]

A Wireless Power and Data Transfer Receiver Achieving 75.4% Effective Power Conversion Efficiency and Supporting 0.1% Modulation Depth for ASK DemodulationDawei Ye, Yu Wang 0046, Yingfei Xiang, Liangjian Lyu, Hao Min, C.-J. Richard Shi. jssc, 55(5):1386-1400, 2020. [doi]

2019

A 340nW/Channel Neural Recording Analog Front-End using Replica-Biasing LNAs to Tolerate 200mVpp Interfere from 350mV Power SupplyLiangjian Lyu, Dawei Ye, C.-J. Richard Shi. iscas 2019: 1-4 [doi]

A 2.4GHz 65nm CMOS Mixer-First Receiver Using 4-Stage Cascaded Inverter-Based Envelope-Biased LNAs Achieving 66dB In-Band Interference Tolerance and -83dBm SensitivityDawei Ye, Rongjin Xu, C.-J. Richard Shi. isscc 2019: 414-416 [doi]

A 2.46GHz, -88dBm Sensitivity CMOS Passive Mixer-First Nonlinear Receiver with >50dB Tolerance to In-Band InterfererDawei Ye, Rongjin Xu, Liangjian Lyu, C.-J. Richard Shi. iscas 2019: 1-4 [doi]

2018

A 13.56MHz Wireless Power and Data Transfer Receiver Achieving 75.4% Effective-Power-Conversion Efficiency with 0.1% ASK Modulation Depth and 9.2mW Output PowerYu Wang 0046, Dawei Ye, Liangjian Lyu, Yingfei Xiang, Hao Min, C.-J. Richard Shi. isscc 2018: 142-144 [doi]

2016

26.2 An Ultra-Low-Power receiver using transmitted-reference and shifted limiters for in-band interference resilienceDawei Ye, Ronan A. R. van der Zee, Bram Nauta. isscc 2016: 438-439 [doi]

A 915 MHz 175 µW Receiver Using Transmitted-Reference and Shifted Limiters for 50 dB In-Band Interference ToleranceDawei Ye, Ronan A. R. van der Zee, Bram Nauta. jssc, 51(12):3114-3124, 2016. [doi]

2013

A wide bandwidth fractional-N synthesizer for LTE with phase noise cancellation using a hybrid-ΔΣ-DAC and charge re-timingDawei Ye, Ping Lu, Pietro Andreani, Ronan A. R. van der Zee. iscas 2013: 169-172 [doi]

2011

A 0.13µm CMOS ΔΣ PLL FM transmitterYing Wu, Xiaodong Liu, Dawei Ye, Vijay Viswam, Lin Zhu, Ping Lu, Dejan Radjen, Henrik Sjöland. norchip 2011: 1-4 [doi]

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